Current Issue

CE Marking

“How to CE Mark Your Product”

Author: Philip King; This email address is being protected from spambots. You need JavaScript enabled to view it..
Abstract: CE marking your new product is not as difficult or as expensive as one might think. Many entrepreneurs worry that the process will drain them of cash, bury them in regulation and paperwork and leave them exposed if they do not do it exactly right. If you are clever about it, it is none of these.

The first thing to understand is that there is no such thing as a perfectly certified CE product. The amount of time you invest in it is up to you, but the responsibility for making sure you have invested enough is also up to you. It is a self-certification process. It will be necessary to make sure the administration is strictly controlled. It must be issue controlled and properly backed up. An enormous amount of money can also be saved by designing for EMC properly and going to the EMC test house properly prepared. (Company white paper, July 2013)


“Guidelines for Ensuring PCB Manufacturability”

Author: Nolan Johnson; This email address is being protected from spambots. You need JavaScript enabled to view it..
Abstract: This white paper discusses ways to troubleshoot a number of common problems in the design-to-manufacture process. It explores a number of straightforward ways to increase the manufacturability of PCBs. It looks at such issues as the mismatch between DfM rules and component footprints, and at integrating backend DfM tools. (Company white paper, January 2014)

IP Protection

“How to Patent a Product”

Author: Philip King; This email address is being protected from spambots. You need JavaScript enabled to view it..
Abstract: If you have an idea and are wondering whether a patent is appropriate, there are three tests to apply to confirm that the idea is patentable: 1. It must be novel. 2. It must be commercially applicable. 3. It must have an inventive step. This white paper gives an overview of the journey from idea to patent. (Company white paper, February 2014)

Package Reliability

“Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs”

Authors: Li-Ren Huang, Shi-Yu Huang, K.-H. Tsai and W.-T. Cheng; This email address is being protected from spambots. You need JavaScript enabled to view it..
Abstract: This paper addresses the testing and characterization of interposer wires in a 2.5-D stacked integrated circuit, which is essential for yield learning and silicon debug. The proposed method provides a number of distinctive features beyond previous works on interposer wire testing. First, the authors target not only catastrophic types of faults (such as stuck-at faults or hard bridging faults), but also parametric types of faults (including both resistive open faults and resistive bridging faults between interposer wires). Second, the method can also be used to characterize the propagation delay across each fault-free interposer wire. (Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, March 2014)

Solder Materials

“Local and Global Properties of a Lead-Free Solder”

Z. Ma, F. Chalon,  R. Leroy, N. Ranganathan and B.D. Beake; This email address is being protected from spambots. You need JavaScript enabled to view it..
Abstract: Elastic and viscous properties, including Young’s modulus, hardness, creep rate sensitivity, and fatigue resistance of Sn-1.2Ag-0.5Cu-0.05Ni lead-free solder, have been investigated. The properties of bulk specimens and in situ solder balls were compared. Experiments show good correlations of Young’s modulus and creep rate sensitivity between conventional measurements and nanoindentation results on bulk specimens. Further mechanical properties of the beach-ball microstructure in solder balls were characterized by nanoindentation. The load-partial unload technique was used to determine variation in mechanical properties with increasing depth of penetration into the intermetallic inclusions in the in situ solder. Fatigue resistances of the bulk specimens and solder balls were compared using the novel nanoimpact method. In comparison with bulk specimens, it was found that in situ solder has higher Young’s modulus, lower creep strain rate sensitivity and better fatigue resistance. The effects of soldering and the scale differences strongly affect the mechanical and fatigue properties of in situ solder. (Materials Science & Technology Conference, October 2012)

This column provides abstracts from recent industry conferences and company white papers. Our goal is to provide an added opportunity for readers to keep abreast of technology and business trends.

Bryan Germann

The mist-based dispensing method is adept at putting micron-sized lines on non-planar surfaces.

Aerosol Jet technology is a fine-feature material deposition solution used to directly print functional electronic circuitry and components onto low-temperature, non-planar substrates.

Aerosol Jet printing functions on the principle of generating a mist through atomization of a nanoparticle colloid solution. Nanoparticle materials liquids, or inks as they are generally called, are made up of nanoparticle solids, solvents and organic binders and even some polymer resins, which are included to make the ink perform on different substrates. These inks must have a certain viscosity and particle sizing in order be printed with aerosol jet. That viscosity is generally less than 500 centipoise (cP), and the particle size must be under 100nm.


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Electronics additive manufacturing can output the same result as conventional PCB methods, but getting there is a much different process.

Read more: Design Implications of Additive Technologies on Circuits

Greg Papandrew

Just like housing, a little extra size can cost a lot more.

Printed circuit boards in panel or array format increase the efficiency of the assembly operation, especially in volume applications. Takt time is greatly reduced, and handling of product is easier. However, rising material prices are cutting into that advantage because more material is required to produce those arrays.

PCB costs are based on the amount of raw material required to make a particular board. The metal finish, like ENIG or silver, plays a part in pricing, but it is the amount of fiberglass and copper needed that really determines the final cost.

The quoted price for most boards in panel or array format is based on a fabricator's desired panel price for a particular technology or quantity, divided by the number of arrays (or pieces) that fit on a standard 18 x 24" manufacturing panel. The more arrays or pieces that fit on the panel, the lower the cost.

Whether that price is dictated by the number of boards (arrays) that can fit on the standard manufacturing panel, or by the total square inches of the finished array, a quarter or half-inch too long in one direction may mean a double-digit price difference.

That price difference is a double-edged sword: Either the board eats into profits because it is costlier to buy, or it’s a missed sales opportunity because the board could have been quoted at a lower cost.

I have seen inefficiently panelized PCBs so many times. Sure, there is always some waste in manufacturing, but how much money is the contract manufacturer throwing away on every assembly?

Maybe that board does need a full inch of material railing on all four sides for it to be assembled, but it’s worth asking whether that was the original array when the assembly was still in its prototype stage. Could it be it was never optimized for production? Did anyone bother to ask?

Buyers who want better panelization pricing must ask:

“Do we have to have railing on all four sides?”

“Does the railing need to be that wide?”

“Can we score instead of route?”

FIGURE 1 shows a PCB placed in an array in one of three configurations, revealing the cost difference realized when the right questions are asked.

6 board buying figure 1

FIGURE 1. A PCB in one of three configurations. Less real estate equals savings.

The tab-routed array on the left with a large railing on all four sides is the least cost-effective design, yielding only 12 arrays per manufacturing panel.

The design in the middle has a much thinner railing, but still on all four sides, with scored spacing in between the boards instead of the route. That half-inch difference in one dimension makes all the difference, permitting 25% more: 15 arrays total per panel.

The design on the right is the most cost-effective, where the PCBs are “butted” up against one another, and just two thin rails are needed along the longer edge. Eight more arrays (a 75% increase) are available from that same manufacturing panel compared to the routed array.

Depending on the board manufacturer, square inches of the finished product can also be used to calculate pricing, especially for larger volume orders, and this illustration holds true for that method as well. Fewer square inches mean a lower cost per array or piece.

Sometimes larger railing is needed, especially if a particular assembly requires something special. An example is a component that overhangs the edge of the board and requires extra spacing. In that case, the PCB buyer’s engineering department should let purchasing know of any special requirements prior to sending them to the fabricator for a quote.

Additionally, board buyers need to talk to their production and engineering departments and ask for a company standard for assembly criteria that can be incorporated into PCB fabrication specs.

Ensure your PCB suppliers have those specs in hand, so the quotes they submit meet your assembly criteria without adding unnecessary costs or delaying quote response times.

The wasted green I see on the production floor is not solder mask. It’s dollars. PCB buyers need to see that too. 

GREG PAPANDREW has more than 25 years’ experience selling PCBs directly for various fabricators and as founder of a leading distributor. He is cofounder of Better Board Buying (; This email address is being protected from spambots. You need JavaScript enabled to view it..

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