Not enough solder? Blame the via design!

Vias in pads can be “solder thirsty” and suck up solder from pads at terminals during reflow, creating what may appear to be solder insufficiency at the joints. This problem is typical of a via-in-pad design. It’s unpredictable as well; solder will randomly tend to fill those vias during the reflow process and some locations may appear worse than others, for example.

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Exhibitors hope new products will keep the order books filled in 2023.

The good times of 2022 carried over into January as the industry turned out for one of the larger IPC Apex Expo trade shows in some time. The San Diego Convention Center show floor was humming for the better part of the first two days of the three-day event, and most of the more than 300 exhibitors seemed pleased with the attendance.

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Some areas of physics have considerable impact on PCB designs.

PCB designers have had exposure to electronics (some more than others). And most of what we do falls under the field of electronics. But designers often have little or no exposure to physics. And some areas of physics have considerable impact on our designs. Here we look at two physical properties of the dielectrics we work with, and why they are important to understand (Note 1).

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Understanding reflections caused by transmission line characteristic impedance and termination impedance mismatch.

Analysis of “digital interconnects” is the analog problem in frequency domain where interconnects are simulated as transmission lines defined by characteristic impedance and propagation constant. Digital signals in interconnects are sequences of amplitude-modulated pulses that transmit bits between components. The “digital interconnect” analysis problem is technically an analog problem of pulse propagation modeling in time-domain.

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