Designer’s Notebook

John Burkhert

Keeping some margin on the table increases the chances of immediate success and leaves a little bit for later.

There are many more ways to constrain a PCB layout than when I started my journey as a semi-intelligent designer. Guardrails were put in place to smooth transition into fabrication once the layout is completed. The other thrust of newer rules concerns the shrinking timing budget of our digital interfaces, particularly the memory banks.

We have so many aspects we can control that it can be tempting to disable or ignore some of them. That is a completely rational choice to make. New features take time to learn and implement. It may not be so easy to get everyone on board for a new feature or a whole new iteration of the software.

I remember getting buy-in to move up to a different whole number revision of the ECAD tools by reminding the team we didn’t have to use any of the new features and could go on using the tool exactly as before. It’s easy to get comfortable with what you have if that gets the job done to everyone’s satisfaction.

What we do is observed by many of the people around us. A narrow focus ends with the various EEs and your management team. Truly satisfying everyone takes a much wider view of the situation. Who is watching? Practically the whole company – and then some.

Read more: Reasons to Go Beyond the PCB Constraints

John Burkhert

Component manufacturers continue to seek breakthroughs, adding functions and reducing size, while fan-out is left to the designer.

While the printed circuit board is composed of sheets of dielectric and conductor layers, it’s the vias that really bring a circuit to life and keep it going. Permitting signals to pass from one layer to another makes this a 3-D puzzle that can scale to a staggering number of layers.

You don’t have to go back many decades to find a time when we called them printed wiring boards. (Officially, the standards still do.) Components were mounted to what looked like a pegboard: rows of evenly spaced holes where the leads of the part extended through two or more of the holes. You just added wire. As far as routing consistency, every board was a one-off, built up one wire at a time.

Give credit to government agencies for driving PCB technology toward higher reliability. Along the way, the “industrial complex” responded with the following electronics innovations:

  • Individual transistors advanced to integrated circuits using dual-inline package technology.
  • Axial- and radial-leaded passive through-hole components gave way to surface mount types with and without leads.
  • Quad flat packages (QFP) and similar devices came along with a full perimeter of signal pins, plus a ground slug taking the central area inside the single ring of pins.
  • Ball grid array (BGA) packages now featured a partial or full field of pins.
Read more: Selecting the Appropriate Through-Via Technology for a PCB Project

John Burkhert

Shortening and folding traces takes creativity and persistence, as long as the timing budget is met.

Printed circuit boards are becoming more complex, with high-speed interfaces more common. Whether it is a PCIe, Ethernet, USB or memory of some kind, clock nets proliferate across the board. Those clocks have kindred spirits in nets that want to hit the receiver in conjunction with the ticking clock.

Crucial parameters of a group of traces include the target length or maximum. Less is more. Most other signals on the board will switch periodically. Meanwhile, the clock switches all the time. The clock uses the same voltage, but the constant stream of “10101010101…” creates more energy fields than a seemingly random sequence of ones and zeros. These constantly shifting reactive clock net fields are the reason we shield the clock, giving it space to do its thing.

Shorter traces equal lower electromagnetic emissions. Shorter clocks have comparatively lower emissions and are less lossy. This gives rise to the use of available length matching tolerance to minimize the length of the clock, starting with finding the longest member of the group. Look at that net; locate any extra bends or places where it can be shortened.

Read more: Length Matching Routing for PCB Busses

John Burkhert

The primary purpose of surface finishes is to prevent oxidation of the copper prior to soldering components.

Back when I held a soldering iron, we used a mixture of tin (63%) and lead (37%) for the solder (Sn63). The boards had the same coating on the plated holes and surface-mount pads. The application for surface mount is referred to as hot air solder leveling (HASL) and applies to any of the available solder types. The beauty of Sn63 is it has a lower melting point and is eutectic. “Eutectic” means the metal solidifies rapidly over a short temperature range. The benefit is fewer disturbed solder joints and good “wetting,” where the surface finish and the solder form a cohesive bond for a reliable connection. You can still buy Sn63 off the shelf at the local electronics store.

On the other hand, lead is a dangerous metal that can cause birth defects and other health issues. The Europeans took the vanguard with the RoHS initiative. If you want to sell electronics products to consumers, the lead content must be the minimum possible – not eliminated entirely but found primarily as a trace element within chips.

SAC (Sn-Ag-Cu): a heroic alloy. Metallurgists all over the world looked for replacement formulas. Tin is still viable and is generally mixed with small amounts of silver and other elements such as antimony, copper or bismuth. Tin makes up the bulk of the alloy, typically around 95% to 99.3%. If pure tin was used, the results could be problematic. Tin whiskers from dendritic growth present a shorting risk.

Read more: PCB Surface Finishes: When to Change It Up

Page 1 of 24