
Given the high cost of silver, it may be surprising at first glance to see low-silver alloys being met with what could only be called lukewarm enthusiasm. Despite the best efforts of Dr. Greg Henshall and a small band of other researchers and engineers, few companies have entered more than the preliminary testing phase.
This was in full evidence at Productronica last month. An unscientific sampling of the more than a dozen solder suppliers there suggests low-silver is not the panacea some had hoped when it was introduced. Why? Primarily because reliability and processing knowledge beat costs.
In case after case, we were informed that interest has been spotty, at best. Reliability in some applications is a question, and assemblers appear, well, fatigued from nearly 10 years of constantly testing and revising lead-free recipes. We know now that no lead-free solder is a drop-in replacement for eutectic tin-lead, a point most solder vendors have quietly stopped pressing. We’ve even heard some Japanese companies are quietly lobbying EU officials to relax the RoHS rules in order to – are you ready for this? – permit the use of solder in a wider array of electronics products. The reason: Tin-lead is more environmentally friendly than the alternatives.
That said, in a year that started out hot and is ending tepid, Productronica was pure gold. The show was a bit smaller from the exhibit side – which is not to say it wasn’t still huge – but veterans will recall when the U-Bahn stopped at both entrances of the massive New Munich Trade Fair Center. Some of those veterans, who will remain me, learned the hard way that the East entrance to the hall is no longer needed. Still, some restraint on the size of the exhibits has long been in order, and we began to witness mild evidence of that this year.
On the show floor, two stories emerged. One is the slow-motion separation of Yamaha and Assembléon, its primary distributor in North America and Europe. Although Assembléon may well sell as many placement machines as any company in the world (once units of its own lines are added in with those it sells on behalf of Yamaha), there is reason to believe a change is coming, and soon. At the show, Assembléon debuted a multifunctional platform called the iFlex, which potentially would compete with the Yamaha lines it reps. Meanwhile, Yamaha has been gearing up to establish a direct US and Europe sales and service presence, hiring staff (including an ex Assembléon manager) and developing a new channel with one of its longtime Asian distributors. It’s remarkable, after so many years of intense competitive pressures, that while some of the pick-and-place vendors have changed hands, none of them has consolidated. Just before the show, Yamaha and Assembléon re-upped their distribution agreement for one year, with an option for one more, but the future of the relationship has never been more in doubt.
On the fab side, robotics were the rage. The PCB fabrication exhibits have shrunk over the years and are now down to about one hall (although exhibitors were spread over two, intermingled with large lounge areas and contract assemblers). Ten years ago, Productronica featured lots of large plating and develop/etch/strip lines and lamination equipment designed for large and heavy backplanes. Meanwhile, machines shown at the CPCA Show in Shanghai could fit in a shoebox. That equation has completely flipped: Productronica is now characterized by ample models of small-scale prototype and batch production equipment. Still, the number and quality of lines far outpaces that of all other Western shows (namely IPC Apex/Expo). (We’ll have the full report next month, or you can check the Productronica 2011 section on the PCD&F and Circuits Assembly websites.)
Each year at this time, CIRCUITS ASSEMBLY names its EMS Company of the Year. Without giving too much away, we had to postpone the announcement one month because our 2011 winner has been busy dealing with a natural disaster. We’ll have the full story in January.
Also every December, this magazine reflects on our friends and colleagues who are no longer with us. While Steve Jobs was the biggest name in tech to pass away in 2011, the person I’ll miss the most is Werner Engelmaier. In my family, the biggest compliment that can be bestowed is to be called “tough.” Through the years I worked with Werner, I never saw him back down or acquiesce when he knew he was right. He always spoke his mind: truth trumped timidity. Werner was tough.
Our best wishes for a safe holiday season.
Some studies have found halogen-containing epoxy resin might produce hazardous carcinogenic gases, such as dioxin and furan, under certain combustion temperatures (i.e., <1000°C).1 Halogen-free flame retardants, which exclude tetrabromobisphenol A (TBBPA), are becoming increasingly popular as a replacement. There are a variety of approaches to replacing TBBPA and other halogenated flame retardants. Among them, the majority of literature focuses on phosphorus-based products, which are predicted to be the largest growing share.2 However, eutrophication of rivers or lakes due to the hydrolysis of the phosphorus-based retardants has raised another environmental issue. Studies conducted by the Institute of Microelectronics indicate that phosphorus-based laminates absorb more than two times as much moisture as conventional laminates.2 Furthermore, phosphorus-based flame-retardants tend to form phosphoric acids under thermal stress, which might be a long-term reliability concern because of acidic degradation.2
With that in mind, we have developed a novel halogen-free, phosphorus-free material (named UP-160HPF) for PCB applications that can fulfill the environmental requirements, exhibit good characteristics and nonflammability without a high cost penalty.
Our objective was to develop a halogen-free, phosphorus-free resin system that contains a large quantity of nitrogen in the main molecular framework. By using a dual-hardener system, which acts as an incombustible-gas generator, the resin system exhibits inherent flame-retardant properties upon curing. Other beneficial characteristics include higher cross-linking density and low coefficient of thermal expansion (CTE). Inorganic fillers with a correct choice of particle size, surface modification and proper dispersion, which can generally display synergistic effects in fire retardancy, were adopted. The flame-retardancy mechanism is known as a heat sink. When exposed to heat, the inorganic filler will decompose to release water vapor, which will cool the system, dilute burnable gases in the flame and create an oxide layer at the interface. The remaining metal oxides form a protective barrier on the polymer surface, shielding it against further decomposition and reducing the amount of toxic gases released.2 The combination of the formula has a flammability rating of UL-94-V0, without additional halogen-based or phosphorus-based flame retardants. The absence of antimony or phosphorus-based flame retardants also fulfills environmental requirements.
Novel Material Properties
Table 1 compares general properties of the novel material with those of conventional FR-4. The higher cross-linking structure of the novel materials results in a higher glass transition temperature (Tg). The near-zero shrinkage characteristic of the unique nitrogen-containing resin system and the dispersion in the resin of some amount of inorganic fillers restrain the z-axis expansion as well. This will lead to higher through-hole reliability.

Although the dielectric constant is slightly higher than that of conventional FR-4, since tan δ is smaller, according to Eq. 1, the transmission loss of conventional FR-4 is almost three times higher than that of the novel material.
α = K * f *ε1/2 * tanδ (Eq. 1)
where
α = transmission loss
K = a factor
f = signal frequency
ε = dielectric constant
Tanδ = dissipation factor or loss tangent.
Thermal resistance. Decomposition temperature (Td) by thermal gravimetric analysis (TGA) is one of the most important measures for determining the ability to withstand Pb-free processes. The TGA of the new resin system (Figure 1) is 40° higher than that of conventional FR-4.

Time to delamination is a test to determine the elapsed time at an elevated temperature, when a sudden and irreversible expansion, indicative of a delamination, occurs. Time to delamination at 260°C (T260) is a common measurement used to assess base material performance. With Pb-free assembly, temperatures of 288°C (T288) and 300°C (T300) are now used to evaluate materials. The T288 results (Figure 2) and (Table 2) indicate the new material is Pb-free assembly capable.


PCB Reliability and Processing Characteristics
Solder float was performed at 288°C for 10 sec. and Pb-free reflow with a 260°C peak temperature up to 15 cycles, respectively. There were no cracks or delamination in the boards under microscope.
Conductive anode filament (CAF) is a conductive copper-containing salt created by electrochemical migration. It is a significant and potentially dangerous source of electrical failure in the PCB.3 The anti-migration test vehicle (Figure 3) was prepared, and the test conditions were temperature=85°C, relative humidity=85%, DC=50V. No CAF was observed even after 2000 hr.

Innerlayer peel strength measurement after oxide processes (with assistance from Jetchem) was conducted per IPC-TM-650 and compared with conventional FR-4 and high Tg material (Figure 4). The results show the novel material’s performance is equivalent to conventional FR-4 and better than high Tg material. No significant differences were observed on peel strength between brown or black oxide. (Oxide chemicals were supplied by Jetchem.) 
Furthermore, desmear process weight loss compared with conventional FR-4 (Figure 5) also shows equivalent results. (Desmear process was done by Jetchem permanganate system with a 12 min. reaction time.) The equivalent results permit more freedom for PCB vendors to design the processes and manage the shop floors.

Conclusion
A novel halogen-free, phosphorus-free material that can fulfill current environmental requirements has been described. The new material has lower dissipation factor, lower CTE (z-axis), exhibits good thermal characteristics and non-flammability without a high cost penalty. It is Pb-free compatible, and the major PCB processing conditions are almost equivalent to conventional FR-4. The new material is patent-pending in the US, Taiwan, Korea, China and Japan.
References
1. G. Söderström and S. Marklund, “PBCDD and PBCDF from Incineration of Waste-Containing Brominated Flame Retardants,” ES&T, vol. 36, 2002.
2. Muriel Rakotomalala, Sebastian Wagner and Manfred Döring, “Recent Developments in Halogen Free Flame Retardants for Epoxy Resins for Electrical and Electronic Applications,” Materials, August 2010.
3. George Morose, “An Overview of Alternatives to Tetrabromobisphenol A (TBBPA) and Hexabromocyclododecane (HBCD),” 2006.
4. D. J. Lando, J. P. Mitchell and T. L. Welsher, “Conductive Anodic Filaments in Reinforced Polymeric Dielectrics: Formation and Prevention,” 17th Annual Reliability Physics Symposium, April 1979.
Christina Jien is a specialist and Johnson Chang is director, engineering & RD operations at Uniplus Electronics Co. (uniplus.com.tw); This email address is being protected from spambots. You need JavaScript enabled to view it..

The majority of surface analysis I use is for troubleshooting, but it is also a critical tool in new product development. We use perhaps two dozen in research and development over the course of a few weeks. The range is quite significant, from x-ray fluorescence (XRF) to understand a metal-plated thickness to much more sophisticated methods, such as Auger for elemental identification.
Knowing the appropriate method to use becomes the greatest challenge. How many times have you submitted a sample for scanning electron microscopy (SEM) and electron dispersion spectroscopy (EDS) that resulted in not finding what you hypothesized or even giving a direction forward?
This month, we offer insight into understanding how the analysis method can be adjusted to gather more valuable information. To discuss all techniques would be beyond our scope, so I will highlight a few and hope to offer some clarity.
XRF is a tool used multiple times a day in circuit board fabrication houses. Each first article is measured by XRF to confirm proper metal-plated thickness. XRFs need to be calibrated daily. This is important to measurement accuracy. Some may not realize that XRF units need application programs to be set up for each substrate being plated. You may think that if you are measuring ENIG on a printed circuit board or a ceramic substrate, you can use the same program. That is not the case. During program setup, the substrate is used; largely different substrates will require different application programs. Using one application for all substrates will result in false thickness readings.
Phosphorus analysis in electroless nickel is difficult for many. I have found that digestion is the most accurate method for such analysis, although it takes a meticulous analyst, as there are many dilutions. Some use XRF or EDS for identification, all methods requiring a standard. XRF suppliers have specialized hardware and software for measuring phosphorus in the EN deposit; not all XRF units are the right equipment for this analysis. Some will give you a number based on the application setup, but this is not accurate. For EDS analysis, I suggest cross-sectioning the deposit and measuring through the section. It is more accurate than a top-down analysis.
Understand the capabilities and limitations of each surface analysis method. This becomes more detailed for more sophisticated techniques such as Auger, XPS and TOF-SIMS. Such methods may not be the best tool for troubleshooting defect panels, especially if the parts have been through an entire manufacturing process or worse, a PCB assembly that has traveled through manufacturing and assembly. You will find every piece of dirt or air contaminant that the board has encountered in its life.
I was recently asked to perform XPS analysis on a product that had been through assembly, product build and functional test to identify the elemental characteristics of the surface treatment. I cautioned the requestor about the instrument sensitivity, noting that using a tool after this much handling can give overwhelming data. Although hesitant, I agreed to move forward, anticipating what could be found. After multiple separate XPS analyses, for which I was distanced from the analyst, the data resulted in more questions than answers. A final set was run with abbreviated assembly and no functional testing. I had to lay out a significant amount of molecular information to a “new to this project” test facility. The final analysis resulted in conflicting information to the previous three, but made much more sense according to the chemical makeup of the coating. There were still pieces of the report not fully understood, but overall, it was a tedious, time-consuming road to understanding pieces of my puzzle were as hypothesized. The moral is that surface analysis on this level gets expensive very quickly, and consulting the experts first and laying all details out upfront is the key to success.
A beautiful display of this was presented at SMTA International this October. The experiment was a combination of mixed flowing gas to create creep corrosion and TOF-SIMS to identify the corrosion product. Some may think the creep corrosion product had been established years ago by Veale1 and confirmed later by Schueller2 and others. The presented material gave further insight into the materials that contribute to the initiation of the reaction. It really was an impressive body of work that will be valuable for the entire industry – well thought-out and executed. Money and resources well spent.
References
1. R. Veale, “Reliability of PCB Alternate Surface Finishes in Harsh Industrial Environments,” SMTAI, October 2005.
2. Randy Schueller, Ph.D., “Creep Corrosion on Lead-Free Printed Circuit Boards in High Sulfur Environments,” SMTAI, October 2007.
Lenora Toscano is final finish product manager at MacDermid (macdermid.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. Her column appears quarterly.
In business, timing is everything. When is the best time for an OEM product or industrial designer to collaborate with their flex manufacturer and assembler? The correct answer should be: “That involvement is an infinite loop that begins during a product’s conception and perpetuates during a product’s evolution.”
In my October column, I focused on how to use flex technology as an enabler to make devices thinner, smaller and lighter. Now, I would like to illustrate an ideal methodology for OEMs to work with the flex manufacturer and assembler to enable technological products that consumers desire.
From my experience, the best flex manufacturers and assemblers provide engineering support early in the product lifecycle, which is typically comprised of six phases:
Concept: When industrial designers determine the desired form factor, features and user experience/interface of their products. This is the architectural stage and flex can play an enabling role.
Design: When product designers complete the electronics and mechanical design to achieve the desired form factor.
Prototype: After the design is complete, the flex manufacturers and assemblers physically create a proof-of-concept product prototype.
Pre-production: Making adjustments to the design to achieve desired performance requirements. The OEM looks to its suppliers to analyze root cause and test when problems are encountered.
Production: Ramping to full production volumes, often very rapidly to match the short marketability of products.
Maturity: End of a product lifespan, when it is ready for next-generation product introduction.
The flex manufacturer and assembler plays an integral role in each of the phases of the product lifecycle. The best flex-product integration is coordinated during the initial stage, which usually results in designs that produce best-in-class devices. It is imperative for any OEM to have early supplier involvement (“ESI”) with its flex manufacturers and assemblers. ESI enables OEM design and supply-chain teams to collaborate with their counterparts during this critical period. ESI provides designers added flexibility with minimal design constraints to maximize 3D packaging solutions. The result is seamless, integrated, flexible – printed circuit assembly solutions that lead to devices that are thinner, smaller and lighter with faster time-to-market.
Despite the best ESI efforts during the NPI stage of prototype and pre-production, engineering changes may be needed to further optimize the design for the desired product performance. In response, flex manufacturers must provide best-in-class program management and streamlined communications to achieve the design that yields the best product. After the design is optimized, the flex manufacturer must have the ability to quickly ramp to volume production, as well as support demand flexibility.
Through the maturity phase of the product lifecycle, the OEM design and supply chain teams would benefit from collaboration with the flex manufacturers to repeat the ESI and NPI phase for subsequent generations of product conception. We call this the “Infinite Loop of Involvement,” and it offers the flexibility to begin the ESI and NPI phase for the subsequent generation of product conception, as soon as the prototype phase of first-generation product is complete.
‘It’s never too early.’ When it comes to involving flex manufacturers and assemblers, one can never get engaged too early. In my experience, the most impressive packaging solutions have come from industrial, product and flex designers co-designing during product conception. That is the necessity of ESI. It is beneficial to proactively think how to use flex to help design thinner, lighter, and smaller products, instead of using flex as an afterthought for a potential fix. Typically, it takes 6 to 9 months to get to production volumes, but with this methodology, OEMs can shorten the process and bring products to market sooner.
It is not enough to just start early. A flex manufacturer should be involved in every phase of a new product’s lifecycle. There must be a culture of collaboration and unison between the OEM design team, the OEM supply chain, and the flex manufacturer and assembler. Once OEMs go through this process and move to a newer product, the loop begins anew. This perpetual cooperation leads to even more advanced, compact and cost-efficient products, and that is a tremendous plus for everyone.

Jay Desai is director of marketing at MFLEX (mflex.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

At least four significant problems contribute to eye collapse and an increased bit error rate in high-speed serial links. Our previous two columns addressed how reflections and losses affect ISI, collapse of the eye, increased deterministic jitter and higher bit error rates. This month we look at how channel-to-channel crosstalk contributes to ISI and collapse of the eye.
Crosstalk from one channel to another can range from as high as 20% in some cases to as low as 0.01% in other cases. And just how much is too much, of course, depends on the received signal strength and how much noise margin is needed at the receiver. In an extreme case, the received signal may be as low as -30 dB from the transmitted signal and still acceptable. If a signal-to-noise ratio of at least 10 dB is desired, then the crosstalk should be less than -40 dB. This is less than 1%.
This is the basis of a simple rule of thumb. Unless you have an extreme channel, the channel-to-channel crosstalk should be kept below -40 dB. If it is ever larger than -40 dB, it may be important to perform analysis to see how much you can tolerate in your specific design.
One reason crosstalk discussions in the literature are so confusing is that so many design factors influence the magnitude of crosstalk. One could easily imagine a situation when it is a killer problem and other cases when it is trivial. It all depends on the specific design conditions and the criterion of how much is too much.
For example, consider a very bad, pathological situation, as illustrated in Figure 1. Two differential channels are routed in long lines in FR-4, but isolated from each other. However, there is a connector or package with 2" of trace in microstrip. Although it is designed as a 100Ω differential impedance, all four signal lines are tightly coupled with a spacing equal to their line width. This occurs very often in flex connector strips.
With a rise time of 25 psec, typical of a high-end PCIe gen II part, and a coupled length of 2", the FEXT would be about 20%. In this pathological
configuration, the far-end noise is generated close to the aggressor TX, so the rise time is the shortest, and the FEXT noise travels to the victim RX very close to the connector, so it suffers little attenuation.
The poor victim RX is at the end of a long, lossy interconnect, so the received signal is attenuated. If the two channels are asynchronous, the noise on the victim line is uncorrelated with the received bit, so the noise will spread uniformly over the entire unit interval.
This 20% FEXT noise, spread over the unit interval, can completely close a marginally acceptable eye, as in Figure 1. In some cases, channel-to-channel crosstalk can ruin your day, and it can arise in board traces, via stacks, connectors, packages and cables.

What can you do to reduce crosstalk to an acceptable level? Table 1 contains some suggestions. But, remember, you have to do your own analysis.

Dr. Eric Bogatin is a signal integrity evangelist with Bogatin Enterprises (beTheSignal.com), a LeCroy Co.; This email address is being protected from spambots. You need JavaScript enabled to view it..

Pad parts change and so do vias. Our standard policy is that open vias in pads are bad. We from time to time recommend ways to plug them. Generally, you have several options, such as capping the top or bottom of the via with solder mask. However, with vias in the pads of really small parts, those solder mask options will probably not work. Solder mask generally isn’t put down with enough precision to cover holes on tiny pads, and further, the solder mask would probably mess with the clearance, especially with very small QFNs. Immersion silver finishes may develop corrosion in sealed vias.
Figure 1 is an example of a small QFP with open vias in the pads. Those are some small vias.

If solder mask isn’t going to work, what will? Filling and plating over them, that’s what. You really have only two choices: fill and plate, or live with a bunch of voids under the part and solder slopped on the bottom side of the printed circuit board.
Figure 2 shows two illustrations representing the issue. In the top half of the image, the vias represented have copper plugs and are plated over by the board fabricator. As with all parts of this sort, there may still be tiny voids. IPC and the manufacturer have guidelines on the maximum allowable voiding. On the bottom, see what happens with the vias left open. Two problems: big voids and solder on the underside of the PCB.

Certainly there are some applications where this doesn’t matter. That’s why there is a second choice: “Live with a bunch of voids and slopped solder.” If you can’t live with voids and solder slop, you have to bite the bullet and pay extra for a PCB with filled vias. Board fabricators that do this have a variety of materials to use, including copper, electrically conductive epoxy and thermal conductive epoxy. Let your board fabricator know what your thermal requirements are, and they can help you choose the right fill material.
Ed.: Read Duane’s blog each week at circuitsassembly.com/blog/.
Duane Benson is marketing manager at Screaming Circuits (screamingcircuits.com); This email address is being protected from spambots. You need JavaScript enabled to view it.. His column appears bimonthly.