Magazine Articles

Pb-free alloys can shorten tip life – but so can poor practice.

During the introduction of Pb-free, solder iron tip damage was very common due to the variability of the plating on some tips. Damage also has been caused by poor control and incomplete operator training; some operators do not recognize the impact of the solder alloy and are reluctant to switch off irons when not in use. Figure 1 shows erosion of the copper core due to lack of protective plating, which may have become damaged due to incorrect use of the iron tip.

If the base material of any soldering tip on irons or desolder stations is exposed to high temperatures and alloys prone to dissolution, this can still occur. If tips are being consumed faster than expected, examine the tip quality. Examine samples before and after use to ascertain the impact on soldering and wetting.

These are typical defects shown in the National Physical Laboratory’s interactive assembly and soldering defects database. The database (http://defectsdatabase.npl.co.uk), available to all this publication’s readers, allows engineers to search and view countless defects and solutions, or to submit defects online. To complement the defect of the month, NPL features the “Defect Video of the Month,” presented online by Bob Willis. This describes over 20 different failure modes, many with video examples of the defect occurring in real time.

Chris Hunt is with the National Physical Laboratory Industry and Innovation division (npl.co.uk); This email address is being protected from spambots. You need JavaScript enabled to view it.. His column appears monthly.

New systems are more robust, faster curing and require less energy than conventional chemistries.

With each passing day, use of silicone rubber is becoming more and more pervasive; products made from silicone are showing up in hospitals, cars, the kitchen and bath, even golf bags. Flexible bakeware and cooking utensils, fuel-resistant hoses and gaskets, airbags and touch pads, shampoos, skin care products and much more are all made possible with new silicone technologies. Dr. Fredrick S. Kipping, the father of silicone chemistry, could never have envisioned the plethora of uses into which his “sticky mess” has grown. From the earliest days of commercialization, silicones have always been selected for any high-performance specialty application that requires durability and outstanding physical properties.

Silicone chemistry is a unique combination: neither purely organic (i.e., carbon-based) nor purely inorganic (i.e., silicon-based), but a molecular-level hybrid of both. The nature of the Si-O bond in the polymer backbone creates low rotation barriers and large bond energies. This inorganic polysiloxane backbone provides the foundation for building materials with superior thermal properties, environmental resistance and flexibility, even at temperatures below -70oC. The methyl groups pendant to the Si-O-Si chain provide for low surface energies, and the low rotation barrier along the backbone permits the polymer to freely orient these groups to the exposed surfaces. The hydrophobic character and soft-touch feel of silicone-based materials is a direct result of this combination.

Silicone elastomers are used as sealants, adhesives and coatings, where they are fluid-applied and cured in place, but may be also molded into a multitude of shapes and used to produce functional products in a range of applications. There are two predominate cure types: condensation-cure and addition-cure. Condensation cure products may be either single-component or dual-component, generally use tin catalysts, require moisture to react and liberate alcohol or other monomers as byproducts during cure. Addition cure materials may also be either single-component or dual-component, are either free radical cured or rely on precious metal catalysts, but perhaps the biggest distinction is that there are no byproducts generated during cure.

Certainly nearly every homeowner is familiar with single-component, condensation cure silicones, perhaps even using some to caulk the bathtub or kitchen sink: the familiar smell of vinegar as acetic acid is liberated during the condensation reaction. Single component, moisture cure, RTV silicones (room temperature vulcanizing) are valued for their ease of use, adhesion, physical properties and environmental resistance. The products are manufactured under dry conditions and stored in moisture-proof packaging. Once applied, the material draws humidity from the atmosphere and begins to cure. The cure proceeds from the outside inward, with the rate of cure determined by the amount of catalyst in the formula, but more important, by the amount of moisture available. The byproduct liberated is dependent on the leaving group of the cross-linker used in each specific formulation (Figure 1).

 

Within electronics, moisture-cure RTVs are often employed as staking compounds, where vibration dampening and stress relaxation are important. These types of staking compounds are most often shear-thinning pastes that, once applied, resist flow and may be used to build up a protective barrier around sensitive components. When fully cured, these materials become relatively soft (i.e., Shore A 25-45), durable, low modulus rubbers. Many silicone conformal coatings are also based on this type of chemistry. The advantages are ease of application, solvent-free formulations and environmental resistance of the cured films. Silicone conformal coatings are most widely used in high-temperature environments, making them the primary choice for under-the-hood automotive applications. However, because moisture from the atmosphere is needed to catalyze the cure single-component, RTVs must only be applied in thin cross-sections, typically less than 0.5", and the assembly must be racked overnight to permit slower cure speeds.

Less familiar, but no less functional, are the dual-component condensation cured silicones where the cross linker and catalyst are contained in separate packages that must be mixed prior to application. Here, the moisture is an integral part of one component, making these formulas much less sensitive to environmental conditions. Also, because the reaction is not dependent on the transport of moisture from the atmosphere, these materials are able to cure in thicker cross-sections. However, a byproduct is still generated during cure, so shrinkage is relatively high.

High consistency silicone rubber (HCR) compounds may be processed by injection molding, compression molding, and extrusion or calendaring. These are the original single-component, addition cure rubbers: typically, ready-to-use blends of silicone rubber with fillers, modifiers and vulcanizing agents that are heat-cured to form elastomeric components. The vulcanizing agents are generally peroxides that break down with heat, generating free radicals that initiate the cross-linking reactions.
Liquid silicone rubbers (LSR) are also based on addition cure chemistry. Generally, two-part pumpable materials that must be mixed and often heat-cured to form elastomers are suited for intricate designs manufactured in large, automated quantities. LSRs rely on precious metal catalysts, usually platinum, to promote cross linking. As with the condensation cure, two-component formulations, the catalyst and cross linker are contained in separate packages that must be mixed prior to application. LSRs and fully-fluorinated LSRs currently represent the fastest growing branches of the silicone family tree.

Platinum-catalyzed, addition-cure silicones may be formulated with an extremely wide range of physical properties and cure characteristics, which makes these materials very popular. One of the most exciting developments is the introduction of low viscosity, optically clear potting and encapsulating compounds. LEDs, photovoltaic subassemblies and other light-sensitive devices require radiation-resistant, non-yellowing encapsulants for protection and improved light transmission. For radiation energy to initiate any chemical changes, causing a breakdown in properties and yellowing, the polymer molecules must first absorb it. Because of the absence of any double-bonds or other ultraviolet (UV) light-absorbing groups polydimethyl siloxane-based, addition-cured silicones absorb very little ultraviolet radiation in the 300-400nm region. As mentioned, the bond strength of silicon-oxygen linkages in the polymer chain is exceptionally high, which prevents oxidation and loss of properties.

In the past, there were concerns that silicone oil migration or bleed out would contaminate sensitive electronic components. Early formulations used silicone polymers that were not stripped of low molecular weight contaminants, and electronic devices relied heavily on mechanical switches. These low molecular weight oligomers could volatize and condense on switches; because silicones are excellent dielectric materials, this could cause poor contact and device failure. Today, silicone polymers go through a much more extensive stripping process to remove and control contaminants. Device design also has improved, so the technology is not as susceptible to any potential contamination.

Heat cure, moisture cure, mixing, ovens: All are fine and effective means for curing products to generate pieces and parts for a great many applications. The real interest and some of the fascinating performance advances are in the field of UV-curing silicone rubbers, with the advantages of speed, ease of application and energy efficiencies associated with traditional UV curing to produce elastomeric materials with all of the performance enhancements of silicone.

The concept of UV curing silicones is not new. Acrylic end-capped, free-radical cure silicones were first commercialized in the early 80s. While they are technically UV cure, these dual-cure systems rely quite heavily on the traditional moisture reaction to affect full cure. The acrylated-silicones are sensitive to oxygen inhibition, require fairly significant energy input to initiate the reaction, and need prolonged exposures to complete the cure. Perhaps because they are not so robust, these materials have not enjoyed the market success of hydrocarbon-based UV cure technologies.

The thiolene “click” reaction is very powerful chemistry. Click chemistry is not one specific reaction, but more of a concept or a philosophy introduced in 2001 by K. Barry Sharpless, Ph.D. of the Scripps Research Institute.1 By definition, click reactions are simple and robust. They use only readily available starting materials, require no solvent, or chemically benign solvents (e.g., water), and proceed to high conversions. Applying these concepts to polymerization reactions yields materials that are extremely dynamic. Thiolene chemistry is the reaction between thiol groups and vinyl functionality. If the molecules involved contain higher functionality (i.e., F(x) >/= 2), then the reaction will produce polymeric materials. The process is normally photoinitiated and proceeds via a very rapid step-growth mechanism; an idealized outline of the initiation – propagation – chain-transfer reactions is shown in Figure 2.


 
In addition to the polymerization reactions discussed earlier, the thiolene reaction may also be used as a cross-linking mechanism. High molecular weight, vinyl functional polymers may be cured with short-chain, or monomeric, multi-functional thiolene curing agents via the same photoinitiated reaction. It is essentially an addition reaction, so no byproducts are produced, and shrinkage is low. There are hundreds of vinyl and thiol combinations. Vinyl functional polydimethylsiloxanes are abundant and readily available, and there is a fairly wide selection of short-chain mercapto-functional polysiloxanes. This combination may be employed to produce UV-cured silicones.2,3 These systems were originally investigated as possible release agents for paper coatings.

This chemistry has been extended to include a secondary moisture reaction for curing in shadow areas and to further increase cure strength, adhesion and system dynamics.4 Clear materials based on this new system are much more robust and cure to greater depths with much lower energy requirements than conventional acrylated silicones. This translates to increased processing speeds and faster turnaround. Essential for protecting electronic circuitry and significantly extending the service life of printed circuit boards, conformal coatings are an integral component of the entire sub-assembly. Eliminating moisture and contamination is a key element for protecting sensitive electronics. Silicone conformal coatings provide an effective barrier, even under the most severe service conditions. Now UV-cured conformal coatings that offer all the enhanced performance characteristics of conventional silicone-based materials, but with higher processing speeds, are available.
Perhaps more important, these new UV-cure, silicone resins may be filled, which means pigmented and even electrically conductive UV-cure silicone products are now possible. Flexible and printed electronics (FPE) incorporate several new technologies and emerging processes and materials across a variety of applications. FPE may be twisted, bent or shaped without damage, enabling endless innovation and unlimited possibilities.

When an application requires performance, durability and physical properties, a silicone-based product is the superior choice. No other chemistry provides the environmental resistance and performance at thermal extremes. While it is true that silicones are critical for applications under the most severe and harsh conditions, it is also true that the enhanced adhesion, increased flexibility and UV and moisture resistance are important for many less-demanding applications.

References

1. H. C. Kolb, M. G. Finn and K. B. Sharpless, “Click Chemistry: Diverse Chemical Function from a Few Good Reactions,” Angewandte Chemie International Edition 40 (11): 2004–2021, 2001.
2. Lee, et al., U.S. Patents Nos. 4,946,874 (1990) and 5,124,212 (1992), Dow Corning Corp.
3. Viventi, U.S. Patent No. 3,816,282 (1974), General Electric Co.
4. Chambers, et al., U.S. Patent No. 7,105,584 (2006), Novagard Solutions.

Brian Chambers is director of technology, Novagard Solutions (novagard.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

Building resistive metal foils on a flex circuit to create heat.

A customer asked if a flex circuit could be made using a metal foil other than copper. They needed to heat a non-flat surface, and wanted the contouring abilities of a flex circuit combined with heating qualities of a resistive foil.

The answer is yes, resistive metal foils can be used on a flex circuit to create heat. Most manufacturers that make resistive flex circuits refer to them as flexible heaters. Many resistive foils can be used for this type of application, as can many different types of adhesive and insulation materials. It is important to understand the differences in the materials used to construct the flexible heater, so that you will know how to properly specify your heater for maximum efficiency and reliability, and also for lowest cost.

While many types of resistive metal foils are available for the construction of flexible heaters, the most common types are cupronickel, constantan (very similar to cupronickel), Inconel and aluminum. The best metal foil type for a given application is driven by the resistance density required. This is derived based on operating voltage and the temperature at which the heater will operate.

Metal foil selection is determined by the amount of resistance needed, and also by the area that that resistance needs to cover. Total heater element resistance is driven by the resistivity of the metal that the foil is made from, the metal foil thickness, and the width of the element conductors. Most flexible heaters are designed to cover roughly 50% of the total heated area with metal. This means that if the heating element traces are 0.020" wide, the spaces between element traces should also be 0.020". This will generally provide the best heat distribution and minimizes the chance for “hot spots” or overheating.

Here is a summary of some common foils and their particular characteristics:

Cupronickel. As the name implies, cupronickel is an alloy of copper and nickel. While there are several types of cupronickel available with different ratios of copper and nickel, the most common alloy for flexible heaters is alloy 715. This alloy is 70% copper and 30% nickel. This material processes during manufacturing in a manner similar to copper, and has the relatively low resistivity of 16.22047 µΩ-inch (for reference, copper is 0.661417 µΩ-inch). This alloy is typically used in applications that don’t require a high-resistance density. One advantage of cupronickel is that it is relatively easy to copper plate to this material. This makes it possible to have a flex heater where certain areas (like power leads) will not heat. Plating copper on select areas of the resistive pattern will significantly lower the resistance in that area, resulting in little or no heat generation. Copper plating also makes it possible to make connections between layers using copper-plated through-holes. When using this technique, the resistive foil typically needs to be on an innerlayer with copper pads (and possibly circuitry) on the outer layers. Cupronickel can be soldered to, making it easy to attach lead wires. Cupronickel has a low temperature coefficient of resistance (TCR), so the heater resistance will change very little as the temperature goes up and down. This makes the temperature much easier to control over a wide range.

Constantan. Constantan is a variation of cupronickel with 55% copper and 45% nickel and a resistivity of 19.63495 µΩ-inch. Constantan is typically used in flex circuit applications such as strain gauges and thermocouples. Constantan also has a very low TCR.

Inconel. There are several alloys of Inconel, but all are predominantly nickel, with chromium as a second element. Iron, molybdenum, niobium, cobalt and other metals are used to create the different Inconel alloys. Inconel 600 is probably the most widely used alloy, with a resistivity of 40.6 µΩ-inch. The high resistivity makes this foil ideal for applications that require a high resistance packed into in a small area. This is a very hard foil that is not easily copper-plated. Inconel is also virtually impossible to solder to, which means that lead wires will usually have to be brazed to the heater element. As with the previous foils, Inconel has a low TCR.

Aluminum. Aluminum foil is generally chosen as a heater element material to save money. The resistivity is roughly double that of copper, and like many other pure metals, it has a high TCR. Aluminum also etches very quickly, which makes it difficult for the manufacturer to keep tight resistance control. But, if you are looking to save pennies and unconcerned about tight temperature control, aluminum may be a good choice.

Picking the Correct Adhesive/Insulation System

The choice of insulation and adhesive is primarily driven by the operating environment of the heater (i.e., operating and ambient temperature, chemical contact, etc.), and to a lesser extent cost. Both the insulation and adhesive type must be rated for the temperatures the heater will be operating at, with sufficient margin to account for temperature excursions. Temperature excursions can be caused by variables such as fluctuating supply voltage and elevated ambient temperatures.
While there are many types of flexible insulation types, and an equal or greater number of adhesive types that could be used to make a flexible heater, a few cover 95% or more of all applications. For insulations, these include:

Polyimide. Polyimide film can be used in a wide variety of flexible heater applications. In addition to being an extremely good electrical insulator (0.001" polyimide has a dielectric strength rating of 7700V), it has also been used successfully in applications at temperatures as low as -269°C (-452°F) and as high as 400°C (752°F). For this reason, polyimide heaters are in use in very low-temperature space/satellite applications, and also in high-temperature applications such as semiconductor manufacturing. The high dielectric strength of polyimide film permits use of film thicknesses as low as 0.001". This results in extremely fast response time and quick transfer of heat from the heating element to the object being heated (usually referred to as the heatsink). Polyimide film also has very good chemical resistance. While polyimide film excels in most of the physical and electrical properties required for a flexible heater, its downside is cost.

Silicone rubber. Silicone rubber heaters combine high operating temperature with moderate price. The most common silicone rubber substrates used for flexible heaters are reinforced with glass fibers to enhance dimensional stability. Silicone rubber heaters can operate continuously at temperatures exceeding 450°F. There is no separate adhesive system for rubber heaters. The base and cover material is generally supplied to the manufacturer as a laminate with cured rubber on one side and uncured rubber on the other. The etched resistive foil pattern is sandwiched between the two sheets of rubber and then laminated to seal.

Polyester (PET). Polyester film is a good choice if the application does not have high temperature requirements and is cost-sensitive. The maximum operating temperature of polyester is less than 225°F. This limitation makes polyester a very distant third behind polyimide film and silicone rubber in total flex heater usage. The relatively low temperatures tolerated by polyester also require special attention be paid to manufacturing processes that utilize elevated temperatures. Special non-standard adhesives may have to be used to bond the foil element to the polyester base and cover.

For adhesives, these include:

Modified acrylic (film). Modified acrylic adhesive is a popular choice for flexible heaters because it is easy to process, has excellent bond strength, and can operate at temperatures of up to 300°F. It is used almost exclusively in conjunction with polyimide film as the dielectric. When processed with good techniques, modified acrylic adhesive will stick well to just about any smooth, clean surface. For this reason, it can be used with all foil types. This adhesive can also be used to permanently bond a finished heater to a heatsink. It is difficult to use acrylic adhesive with polyester because the temperature needed to cure the adhesive would melt or significantly soften the polyester.

Modified epoxy (film). Modified epoxy adhesive is very similar to modified acrylic, and in most cases, the two adhesive systems are interchangeable. Acrylic and epoxy adhesives look the same, process the same, and perform very closely in the finished product. A notable difference is that epoxy has a very slight edge on temperature and chemical resistance over acrylic. US manufacturers tend to lean toward acrylic adhesive, while Asian manufacturers favor epoxy adhesive. Like acrylic adhesive, epoxy adhesive is difficult to use with polyester and is used mainly in conjunction with polyimide film as the insulator.

Teflon (FEP). Teflon adhesive is used in applications that require the material to tolerate either very high or very low temperatures, or both. While this material can operate from less than -300°F to nearly 400°F, its selection significantly reduces the number of vendors that can build the heater due to the high processing temperatures.

Polyimide adhesive. B-stage polyimide is typically supplied to the flex heater manufacturer in the form of a laminate in which adhesive is coated to one side of a sheet of cured polyimide film. This material is the most expensive of the commonly used adhesives, and is also the most difficult to process due to the high lamination temperatures required for curing of the B-stage adhesive. As with FEP, specifying this material will significantly reduce the supplier base. Once cured, polyimide adhesive can withstand much higher temperatures (up to 500°F) than any of the other adhesives.

Heater Design Considerations

Once the materials to construct the heater have been selected, the next step is to lay out the heater element pattern(s). Most heaters will have a single continuous element that serpentines around the heater area, but some heaters will have multiple elements that can be controlled independently from one another for precise temperature control.

The heater element artwork layout requires the heater designer to fill up the area to be heated with uniform conductor pattern(s) that will yield the necessary resistance. Heater element patterns can also be profiled with smaller traces in areas that require more heat and wider traces in areas requiring less heat. As mentioned, selective areas of the heater element can be plated with copper (on cupronickel and constantan) to significantly reduce the heat generated in those select areas.

Once the heater material selection and heater element layout are complete, manufacturing is relatively straightforward. The flexible heaters are processed much like single-sided flexible circuits. The heater element traces are defined using a photo-etch process, and then the cover insulation is laminated in place with heat and pressure. Prior to laminating the cover insulation, many heaters will have lead wires soldered, welded or brazed to the heater element.

Terminations. On the vast majority of flexible heaters, power is supplied via lead wires that are welded, brazed or soldered to pads on the heater. Connectors can be used in applications where the foil can be soldered (i.e., cupronickel, constantan, etc.). Also, insulation displacement contacts can be a cost-effective and reliable means to bring power to the heater. Because these contacts do not require soldering, they can be used on all types of resistive foil. When using insulation displacement contacts, heater foil thickness should be at least 0.002" for ease of manufacturing.

Mounting to heatsink. The final step to complete the heater assembly is to attach the heater to the item to heat (heatsink). This can be done by either the end-user or by the flex heater manufacturer. Probably the most common adhesive used to mount a heater to a heatsink is an acrylic or silicone-based pressure-sensitive adhesive. It is very important to ensure that the heater is mounted to the heatsink with no voids or air bubbles between the heater and the heated surface. These voids will keep the heat generated by the element from being transferred to the heatsink efficiently. This in turn can cause isolated hot spots in the heater element. If the hot spot is large enough, the resulting temperatures can cause the heater element to burn out like a fuse. For this reason, most heater users prefer to have the flexible heater mounted by the heater manufacturer.

And I would be remiss if I did not mention that the folks that build these products are the experts. They can assist in material/termination selection, element layout, and heater attachment methods. Engaging them early in the design offers the greatest chance of success on a heating project.



Mark Finstad is senior applications engineer at Flexible Circuit Technologies (flexiblecircuit.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

Effects of passive geometry or topography attributes common to PCB layout.

High-speed signal integrity is often influenced to a greater extent by the printed circuit board’s physical parameters than the chosen laminate material. High-speed laminate materials with a low dielectric constant or permittivity, , and dissipation factor, , determine signal propagation velocity, dispersion and attenuation. While these two parameters,  and , certainly influence high-frequency attenuation and circuit rise time, their effects may be compensated for through pre- or de-emphasis and equalization. Through the application of glass styles, high-speed laminate properties are becoming more isotropic. Upon selecting a laminate material, the and remain static. Thus, the remaining variables are those associated with the PCB layout. The purpose of this discussion is to identify various passive geometry or topography attributes common to the PCB layout, their effects and potential corrective actions.

Impedance discontinuities, channel-to-channel crosstalk, skew, and unwanted reflections associated with the PCB geometry or topography adversely influence gigabit transmission clarity. Those traces exceeding the critical length associated with signal rise time behave as transmission lines. The need to apply transmission line concepts may be ascertained by defining the signal path critical length. The propagation velocity, conversely the propagation delay, , and critical length may be calculated as follows, where is the speed of light and is the dielectric constant at the operating frequency:







The critical length may be estimated by calculating the distance a pulse travels in one-half the rise time of the logic device or family selected:



Outer layer traces, which are subject to the PCB plating process and have a metalized surface finish delineating the traces during the etch process, may have undesirable magnetic properties and a greater delineation tolerance than that seen with an innerlayer trace. Due to improved trace delineation, reduced electromagnetic interference, and not being influenced by a metalized surface finish, transmission line innerlayer traces are often preferred.

Passive interconnect losses and signal distortions may be classified per Table 1. The dissipation factor or loss-tangent and skin depth effects associated with a conductor’s cross-section and surface roughness drive frequency-dependent losses. The most prominent would be loss attributed to dipole oscillation within the laminate material.





Conductor loss varies proportional to the square root of the frequency:



As a fast rising edge propagates, fewer high-frequency components remain, and the rise time increases. This is the chief cause of inter-symbol interference, ISI. Corrective actions include:

  • Increase conductor width.
  • Lower dissipation factor.
  • Pre-emphasis (High-frequency addition).
  • De-emphasis (Low-frequency reduction).
  • Equalization (Add frequency-dependent gain at receiver).

Impedance discontinuities associated with trace routing reflect a portion of the signal being transmitted and contribute unwanted transmission line noise and ISI. Reference plane geometry and continuity, trace width variations, and the plated through-hole (PTH) and via structures may contribute to reflections. Corrective actions include:

  • Microstrip and embedded-microstrip having an uninterrupted and electrical stable reference plane, minimum pad diameters and vias, and avoidance of abrupt modifications to the trace geometry, such as 90° turns.
  • Stripline and offset stripline trace routing should employ similar parameters as recommended for microstrip and embedded-microstrip.
  • Ground planes should have low impedance returns, reducing the opportunity for ground bounce and common mode interference.
  • Avoid ground planes with rectangular slots, square openings and placing embedded traces within the plane.

Routing trace connections through an impedance-compensated via or PTH providing a connection between multilayer signal traces minimizing capacitance and controlling via or PTH stub length reduces reflections emanating from layer-to-layer connections. While the ideal PTH or via connection may not often be achievable, the following may be employed to assist signal clarity:

  • Minimize PTH capacitance by removing non-functional pads.
  • Minimize via and PTH diameter and associated pad.
  • Maximize anti-pad clearance.
  • Minimize PTH stub and avoid having a stub whose length is a quarter wave length.
    • Wave length.
    • Length.
  • Stubs shorter than 0.050" appear capacitive and slow down the edge rate.
  • Stubs longer than 0.050" act as resonators.


Channel-to-channel crosstalk is both capacitive through electrical field coupling and inductive through magnetic field coupling. Capacitance-coupled crosstalk has the same polarity as the active signal. Inductive-coupled crosstalk at the driver or near end has the same polarity as the active signal and the opposite polarity at the receiver end. Near end crosstalk (NEXT) or backward crosstalk is the sum of both capacitance and inductive coupling, and thus of greater magnitude than far end crosstalk (FEXT). Coupled trace lengths beyond which crosstalk contributes to signal interference:

NEXT

FEXT 

Minimizing crosstalk can be achieved by:

  • Microstrip with spacing between adjacent single-ended traces and/or adjacent differential pairs greater than twice the distance to the reference plane.
  • Offset stripline with spacing between adjacent single-ended and/or differential pair traces greater than twice the distance to the closest reference plane.
  • Symmetric stripline with spacing between parallel single-ended and differential pair traces greater than the distance to the reference plane.

In addition to closely spaced parallel traces, via fields may also contribute to crosstalk. Minimizing stub length reduces reflections and unwanted via field crosstalk. Alternating via pairs in a via field, such that every other via pair’s coupling is at 90° to the previous contributes to reducing crosstalk.

Intrapair skew resulting from time delays associated with differential pairs is driven by:

  • Difference in conductor lengths between differential pair traces and can be avoided through proper routing, assuring individual trace length equalization.
  • Another source, the difference in between the glass weave and laminate resin affects the average signal propagation velocity between traces within a differential pair and contributes to oscillating impedance shifts. The glass and resin varies from approximately 6.0 to 7.0, and 2.5 to 4.0, respectively. Traces predominantly referencing glass having a greater  will have a lower impedance and greater propagation delay than those traces predominantly over resin.

Minimize intrapair skew:

  • Selecting a class style providing a homogenous weave and reducing the potential to have each trace within a differential pair inadvertently routed continuously over substrate regions having different values.
  • Placing the backplane or system card on a process panel to maximize opportunity for traces within a differential pair to have an equivalent distribution, considering the laminate’s epoxy and glass weave structure.

The system noise budget with respect to gigabit speeds and subsequent bandwidth and bit error rate will determine the need to apply the material and physical principles discussed. If the laminate material has a characteristic loss tangent or dissipation factor and skin depth losses within the copper trace, signal strength decreases with increasing frequency. And noise increase with increasing gigabit speeds through crosstalk, impedance mismatches, unwanted reflections radiating from via or PTH stubs, and skew. The object of a circuit board design is to preserve signal strength and clarity and reduce opportunities for distortion and noise resulting from the printed circuit board material and physical parameters.

Bibliography

1. H. Johnson and M. Graham, High Speed Digital Design: A Handbook of Black Magic, Prentice Hall, 1993.
2. T. Edwards, Foundations for Microstrip Circuit Design, John Wiley and Sons, 1983.
3. C. Coombs, ed., Printed Circuit Handbook, McGraw-Hill, 1995.
4. R. Pangier and M. Gay, “Making Sense of Laminate Dielectric Properties,” Printed Circuit Design & Fab, January 2009.
5. G. Ravindra, “PCB Dielectric Materials for High Speed Applications,” Printed Circuit Design & Fab, December 2008.
6. D. Brooks, “The Skinny on Skin Effects,” Printed Circuit Design & Fab, December 2009.
7. J. Coonrod, “Understanding PCBs for High Frequency Applications,” Printed Circuit Design & Fab, October 2011.
8. J. Howard, “Quadrature-VIA layout,” EDN, December 2011.

Carl F. Hornig is a retired engineer who most recently worked at Sanmina-SCI’s backplane division; This email address is being protected from spambots. You need JavaScript enabled to view it..

Key aspects of ATE platform boards and how an IPC test panel design is used to qualify suppliers.

ATE platform boards are simply defined as interfaces used between a semiconductor device and an electrical tester. They include necessary circuitry for device testing and can also dock to a robotic handler for running high-volume production. Handler applications vary, generally manipulating either a semiconductor wafer (probe test) or an IC device package (final test).

Development stages of an ATE board include design, fabrication and assembly. The challenges and significant characteristics of making ATE boards put them into a distinctive category in PCB manufacturing. Some common considerations of ATE board fabrication include:

Via aspect ratio. Typical ATE board thickness requirements range from 0.125" to 0.250" (3.175 to 6.35mm). This board thickness is used primarily for mechanical stiffness. High layer counts are necessary for some test solutions, which results in a large board thickness in addition. The number of layers within an ATE board can be greater than 40.

The substantial thickness of an ATE board leads to electrical interconnect vias having a high aspect ratio. (Aspect ratio is defined as a via’s drill depth over its drill diameter.) As via aspect ratio increases, it becomes more difficult to achieve adequate copper thickness plated along the hole wall, especially at the barrel center.

Sequential lamination. Many PCBs are manufactured with only one lamination step (or press-cycle) to fuse all its layers together. Sequential lamination involves creating two or more multilayer boards first and subsequently pressing those together to form a single board.

Complex builds may require additional lamination cycles and might also use microvia buildup layers. This can lead to a particular board section undergoing two to five cycles in the press. Multiple lamination cycles are common for ATE boards. Reasons this is incorporated include aspect-ratio reduction, limited drill-bit flute lengths, and microvia buildup layers.

Multiple lamination cycles can cause a board to be more susceptible to delamination. Board delamination may not be apparent until after a component assembly reflow cycle or perhaps upon inspection after failure in the field.

Registration. Registration is loosely described here as the vertical alignment of PCB features on different layers. It is a critical aspect for attaining layer-to-layer electrical interconnects. Misregistration occurs during the PCB build process for numerous reasons. High layer counts, multiple lamination cycles, small PCB features, and errors compensating for material movement (that occurs during lamination) all contribute to the likelihood of registration failure.

While often viewed as a consideration for achieving a desired electrical interconnect, registration can also be thought of as an amount of drill-to-copper clearance necessary to maintain a desired electrical isolation. Drill wander is a separate issue, but its net effect results as a misregistration problem as well.

Multiple PCB features and technologies. ATE board designs can require multiple PCB features, feature sizes and process technologies. In that case, a fabricator must be capable and proficient with all. Specific technology requirements might include laser microvias, blind and buried vias, fine lines and spaces, backdrill through-holes, vias plated shut, partial-depth via plugging, selective NiAu finish, and very high layer counts. Other ATE board requirements can also involve atypically low tolerances for controlled impedance, positional accuracy, bow and twist, and relative copper feature height.

Resilience to mechanical and thermal stresses. Electrical interface to ATE boards is generally accomplished using spring-loaded pogo pins, which can number in the thousands on a given board, exerting a minimum of 25g of force per pogo pin. Pogo pin forces occur at both the electrical tester interface and the interface to the device(s) under test.

Docking to a robotic handler can also exert substantial forces on an ATE board. All these mechanical forces are typically dealt with using a combination of board thickness, metal stiffeners, and support plates.

Of even greater concern are the temperatures at which an ATE board might need to be subjected. Semiconductor device testing can have temperature requirements in the -50°C to 200°C range. A PCB expands in all directions as its temperature increases. Particularly stressful on an ATE board is thermal expansion in the z-axis, which can lead to via failure and board delamination.

In addition to the manufacturing challenges described, other characteristics of ATE boards contribute to their overall nature and drive further considerations. Factors including low quantities, long manufacturing times, and high cost and criticality not only impact board fabrication, but also affect decisions related to parts kitting, component assembly, post-assembly testing and end-user planning.

Evaluating ATE Board Fabricators

Because of the manufacturing challenges and critical nature of ATE boards, a non-subjective, quantitative approach is necessary when considering a fabricator’s capabilities, process quality and product reliability. A supplier site audit is not adequate, regardless of onsite equipment or plant cleanliness. Qualification practices based on examining sample coupons or accepting functional boards for evaluation have considerable limitations. Sole use of such methods invites risk to the semiconductor device manufacturer when qualifying an ATE board supplier as a link within this supply chain.

These quantitative measures described need to be obtained using a test vehicle that closely represents the end-product.1 In doing so, most manufacturing processes typically applied need to be included, even if more expensive, time-consuming and challenging. Statistical significance is important for reducing risk. Not many years ago, a race among PCB fabricators began in order to boast the highest aspect ratio through-hole via. Very high aspect-ratio claims made their way onto capability lists within manufacturer websites. The fact that a very high aspect ratio via is able to be produced does not indicate anything about its physical properties, predicted yields, manufacturing repeatability, and reliability under stress. As that became apparent to end-users, most fabricators have since removed statements of 30:1, 40:1, and even 50:1 aspect ratio capabilities.

Beginning in 2006, we adopted the use of standardized test panels to quantify capability, process quality and product reliability of existing and potential ATE board suppliers. The test panel design was selected to align with typical ATE board requirements. It is a 24-layer, multi-lamination build using an 18" x 24" (457.2 x 609.6mm) panel. It incorporates six via types, each built using two different drill diameters: through-hole, back drill through-hole, blind mechanical, buried mechanical, one-layer deep microvia, and two-layer deep microvia.

Test panels also include four plated-layer trace widths ranging from 0.003"-0.006"  with three spacings of 0.004"-0.006." Four non-plated trace widths range from 0.002"-0.005" with three spacings of 0.003"-0.005." Controlled impedance is evaluated for 50Ω single-ended lines and 100Ω differential pairs on surface microstrip, embedded microstrip, and stripline. Coupons testing soldermask registration and conductive anodic filament are also utilized.

A test panel submission consists of 15 test panels manufactured in three equally-sized lots with no less than one week between the start of each lot. Requirements to achieve ATE board alignment include a target thickness of 0.187" (4.75mm), electroplated NiAu surface finish, and typically specified laminate materials. All manufacturing processes must reside within the facility producing the test panels. Disclosure is required if any outsourcing is used. Supplier results include quantifications in terms of defect densities as defects per million vias (DPMV) and defects per million inches (DPMI), percent registration yields, process variations as coefficient of variation (COV), capability potential (CP) and capability performance (Cpk), thermal cycles to 10% resistance change / open circuit, and hours to conductive anodic filament (CAF) failure.

Table 1 highlights the number of features both on this test panel design and the full submission quantity.



Suppliers are expected to complete the 15-panel set in about three months. Third-party testing takes one to two months to complete.

Latest Test Panel Study Results

Some notable observations from our supplier’s most recent test submissions include the following:

Via daisy-chain defects indicate 0.010" diameter, 18:1 aspect ratio through-hole vias continue to prove to be challenging for some suppliers.2 We found 0.012" diameter, 15:1 aspect ratio through-hole defects are better by a factor of at least three times, but results vary significantly among suppliers. Test panel cross-section photos revealed inadequate hole wall copper plating for both 18:1 and 15:1 aspect ratio through-holes in some cases. Figures 1 and 2 are test panel cross-section examples of good and poor through-hole copper thickness.



Test panels place registration coupons at each corner and amid the central area. Through-hole registration results are provided in terms of percent yields within an allowed radial distance outside a 0.012" drill diameter. Radial distances in this case measure from 0.003" to 0.008" given in 0.001" increments. Test data expectedly show that results are significantly better at the center area of the panel. It may be desirable to consider central panel registration results vs. panel corner results separately, especially in cases when boards are fabricated far from the corners. Combining test results from all areas, the greatest supplier results range for 0.012" through-hole vias was at the 0.006" radial distance.

Thermal cycle testing is performed similarly on all via structures used in the panel design. After test coupons are subjected to six passes of a 260°C assembly simulation reflow profile, they are placed in an air-driven temperature cycling chamber that attains extremes between -40°C and 145°C.3 Next, 4-wire resistance measurements are taken across via daisy-chain structures during cycling. Specifically noted is the number of cycles until 10% resistance change and cycles to open circuit, defined as 20Ω or greater.

Test results show thermal cycle performance does not always correlate to defect density. A supplier may have good defect density results, but poor thermal cycling performance at the same time. Significant differences were demonstrated between the 18:1 and 15:1 aspect ratio vias. 15:1 aspect ratio through-holes attained at least two times the number of thermal cycles achieved by 18:1 aspect ratio vias.

Mechanical blind vias on this test panel are 10-layer, 0.008" and 0.010" drills with aspect ratios of 6:1 and 5:1, respectively. Mechanical buried vias are four-layer, 0.006" and 0.008" drills with aspect ratios of 3:1 and 2.5:1, respectively. All areas of blind and buried via testing, including defects per million vias, registration yields, coefficient of variation, and thermal cycling show significantly higher performance than the through-hole via test results from all suppliers.

Use of lower aspect ratio blind and buried vias combined with sequential lamination and lower through-hole aspect ratios is the preferred build method for ATE boards over the use of high aspect ratio through-hole vias and no sequential lamination cycles.4

One-layer deep microvias utilize 0.003" and 0.004" drills with aspect ratios of approximately 1:1 and 0.75:1, respectively. Two-layer deep microvias utilize 0.007" and 0.008" drills with aspect ratios of approximately 0.85:1 and 0.75:1, respectively. One-layer deep, 0.003" laser drill defect densities continue to be at least two times higher than the 0.004" drill. Supplier results range widely among both drill diameters.

Both two-layer deep microvia drill diameters have significantly better defect densities than the one-layer deep microvias, but supplier ranges still vary widely. There appears a correlation of better results when in-house laser drill is performed vs. outsourced laser drill. Outsourced laser drill is demonstrated to have acceptable results, but considerations in regard to where post-processing and plating is handled should be made, especially if buildup microvia layers are used.

Laser microvia thermal cycling results demonstrate much higher performance than through-hole vias, achieving similar results as the 10-layer mechanical blind vias.
Conductor and space test results are provided for three different layer-types: plated outer layer, plated innerlayer and non-plated 0.5 oz. innerlayer. Plated outer-layers have a surface finish of electroplated NiAu specified at a minimum 200µin nickel underneath 5-15µin gold with Knoop hardness from 130-200. Plated innerlayers are a result of the sequential lamination build in this case and do not have a surface finish.

A conductor defect is simply a measurement of an open, and similarly a space defect is measurement of an adjacent short. Conductor defect densities on plated and non-plated inner-layers tended to be acceptably low, with a few supplier excursions seen on the smallest respective widths. Result ranges were observed to be much greater on the outer-layer conductor defects, especially with the smallest 0.003" trace width. Figure 3 shows four different supplier examples of the outer layer 0.003", 0.004", 0.005", and 0.006" conductors. Notably, significant differences are seen among all four examples in terms of copper trace etch factor, NiAu thickness, and length and shape of NiAu overhang.



More commonly encountered in ATE board development are space defects, especially when fine pitches are involved, and the test data reflect this. High supplier result ranges are observed on all layer types, especially at the smallest widths tested. Among all suppliers, the highest space defects occur on the plated outer layers. While defects per million inches is substantially highest with the 0.004" spacing and incrementally decreases by whole factors at both 0.005" and 0.006" spacings, very large ranges within supplier results are found on all outer layer space widths. Outer layer space defects were observed on test panel cross-sections (Figure 4).



Managing Test Results Data

After receipt of supplier analysis reports, two applications of the data used are a scoring system and design for manufacturability rules. Developing a scoring system for supplier test panel results is advantageous for many reasons. The number of test results for each individual supplier is extensive. Such a system can be used to simplify data analysis and supplier comparisons. Different scoring weights can be allocated to areas according to the greatest emphases for ATE boards. Ranges for acceptable high and low ends of test results should also be included. Scores are used to identify weak areas and promote competition among suppliers without revealing one’s specific test results to another. Board fabricators can be told non-subjectively where they placed among the supplier base.

Allocating Weights


Level 1: The scoring system developed here is based on a 0 to 5 point overall scale. Many different test panel features, feature sizes, and test types require approaching the results on different levels. Level 1 represents the five highest test areas examined on this panel design: mechanical vias, laser vias, trace and space, controlled impedance and soldermask registration.

Based on the 5-point maximum, each area is allocated the weights shown in Table 2. Mechanically drilled vias are understood to be the weakest link in a high-performance ATE board and receive 40% of the total points. Trace and space and controlled impedance each get 20%, laser vias 15%, and soldermask registration 5%. Historically, soldermask registration capability has not strongly impacted ATE board development, but will likely become more important as component densities continue to increase.



Level 2: Level 2 separates these five areas into their specific feature types. For example, mechanically-drilled vias comprise four different structures on this test panel design: through-holes, backdrill through-holes, 10-layer blind and 4-layer buried. Considerations for the amount of weight to apply to each feature type can include Difficulty to Produce, Frequency of Use, Susceptibility to Failure, and Supply Chain Availability. Table 3 is a breakdown of the five high-level test areas in terms of their feature types and shows the allocated weights assigned to each.



Level 3: Level 3 is the final level and involves specific test panel results. Feature types are further separated in Level 3 by two factors: Type of Test Performed and Feature Size. Six test types are considered for the through-hole vias: defects per million vias, registration, coefficient of variation, thermal cycles to 10% resistance change, thermal cycles to open circuit, and hours to CAF failure.

Considering the two through-hole drill sizes used, 0.010" and 0.012", 18 total test results are applied here for the through-hole feature type. Table 4 is an example of the Level 3 weights assigned for the through-hole via feature type. As with Level 1 and Level 2, weight allocations for specific test types and feature sizes can be based on several factors. In this example, the test types of defect density and registration are each allocated 30% of the total weight, thermal cycling 25%, process variation 10%, and CAF 5%.



All different feature sizes have their allocated weights split evenly in this example, but that does not have to be the case. Emphasis may be placed on feature sizes more difficult to produce or perhaps feature sizes most commonly used.

After weights are assigned to all individual tests, acceptable test result ranges are indicated and used to determine the supplier’s score on a specific test. A supplier’s result is compared against the acceptable range, and then a weight factor is determined. The weight factor is based on where the test result falls within the acceptable range.

Table 5 is an example of the 0.002" radial distance microvia registration for the one-layer deep feature. Here, five supplier test results are shown as A-E. The allocated weight for this test is 0.01875 points, and the specified acceptable range is 60% to 100% yield. In this case, the target is a maximum 100% yield. If a supplier achieves the target result or better, the entirety of the allocated weight is awarded. If the test result is at the farthest end of the specified range or worse, the supplier receives no score. When the result falls somewhere within the acceptable range, the supplier receives a percentage of the allocated weight determined by position within the range. In the example, a test result of 70% yield would earn 0.25 times the allocated weight; 80% yield would earn half, and 90% yield would earn 0.75 times the allocated weight.



This scoring system is applied to a total of 212 test results for each supplier. Table 6 depicts highest and lowest scores achieved at Level 2 for six suppliers using color coding. Ranges between high and low scores are appreciable in all cases. The table demonstrates that no single supplier exceeds nor fails in all test aspects.



ATE Board DfM


Supplier test results can also be used as the basis for a DfM rule-set. When a multi-supplier strategy is incorporated, test results can certainly be used to determine recommended suppliers based on specific board build requirements. DfM rules should be implemented globally however. This ensures board designs are not limited to single-source manufacturability or perhaps a very limited number of suppliers. Whenever possible, the same aspect should apply such that novel, single-source technology capabilities are avoided if at all possible. DfM minimum and maximum constraints are used to establish quantified limits for improving fabrication yields. Whenever a design allows, absolute minimums and maximums should always be avoided and the number of their occurrences limited.

Mechanically drilled vias with high aspect ratios. As noted earlier, mechanically drilled vias with high aspect ratios have implications that go well beyond a supplier’s ability to merely produce them. This is considered to be the most critical DfM rule to be specified for ATE boards.5 Prohibition of techniques such as flip-drilling, used to attain very high aspect ratio vias, might also be considered. Regardless of how well a supplier can demonstrate the ability of such a process, the result is still a very high aspect ratio via requiring sufficient plating thickness.

Maximum laser drill microvia aspect ratio. Most suppliers specify a capability range between 0.7:1 and 1:1, with 1:1 commonly identified as “engineering level”.

Prohibit mechanical depth drilling for plated vias. The technique of creating blind vias without drilling entirely through a board has proven to yield very poor results in terms of defect density, process variation, and thermal cycling.

Mechanical drill hole wall to hole wall spacing. Drill wander, material properties, wicking, and susceptibility to CAF failure are some considerations in determining this specification.

Mechanical drill hole wall to copper feature spacing. This specification should vary depending on the depth of drilling involved. Test panel registration results provide a good basis for this.

Laser drill hole wall to copper feature spacing. Test results indicate a significantly smaller spacing is feasible among most suppliers than with minimum mechanical drill hole wall to copper feature spacing.

Copper feature to copper feature spacing. Fabricators may indicate this capability as a general minimum to be applied within an entire board, but supplier test results indicate consideration may be necessary for different cases of plated outer layer, plated innerlayer, and non-plated innerlayer.

Supplier Improvement Trends

After test panel data is received, supplier debriefs completed, and improvement plans are communicated, a common question is, Are the board fabrication suppliers getting better? Charts of average defect density trends for through-hole, blind, buried, and laser microvias all indicate supplier improvements. The following graphs represent our specific supplier test panel submissions. It should be noted they are not a representation of the entire PCQR2 database and all suppliers that participated within it.

Figure 5 shows that average supplier 18:1 aspect ratio through-hole DpMV has decreased since 2006 from a high of 3,009 to 1,234 from the latest test submissions. Average 15:1 aspect ratio through-hole DpMV ranged from highs of 643 and 708 in 2006 and 2008, respectively, to lows of 375 and 402 DpMV in 2009 and 2010, respectively.



Figure 6 shows 10-layer, 0.008" blind vias had an average supplier defect density of 416 DpMV in 2006. This decreased to 11 DpMV by 2010. For four-layer PCBs with 0.006” buried vias, the average supplier defect density was 425 DpMV in 2006, decreasing to 5 DpMV by 2010.



Finally, 0.003", one-layer deep microvia DpMV fell from a supplier average peak of 2,882 in 2008 to 867 DpMV in 2010 (Figure 7). And 0.004", one-layer deep microvia DpMV fell from an average peak of 1,512 in 2008 to 395 in 2010.



Conclusions


Benchmarking and qualifying PCB fabricators for semiconductor test boards requires a quantitative, statistically significant approach that otherwise invites unacceptable risk. Standardized test panels provide a sound basis for engaging with the supplier base and participating in continuous improvement plans. Over time, test panel results objectively demonstrate if suppliers are attaining agreed-upon goals. Since the test panels are close representations of the end-product, it is reasonable that measured process capability, quality and reliability improvements directly impact the fabrication of our ATE platform boards, contributing to maximum entitlement of semiconductor device manufacturing.

Acknowledgments

The author would like to acknowledge the support of Texas Instruments in this ongoing effort, and thank you to Mike Korson in particular. Thanks also to Norm Armendariz, John Hite, Pete Profilet, Martin Gao, Stan Ferrell, Jim Oborny and Marc Mydill. The author would like to acknowledge and thank the support of David Wolf and Tim Estes of Conductor Analysis Technologies. Special thanks to the IPC PCQR2 Database D-36 Subcommittee and all Texas Instruments’ ATE platform board fabricators.

References

1. D.L. Wolf, “Via Reliability – A Holistic Process Approach,” SMTA International, October 2009.
2. Bill Mack, “Benchmarking Printed Circuit Board Fabrication Suppliers Using IPC’s PCQR2 Database,” Burn-in & Test Socket Workshop Proceedings, March 2007.
3. IPC-9151C, “Printed Board Process Capability, Quality, and Relative Reliability (PCQR2) Benchmark Test Standard and Database,” May 2010.
4. Kevin T. Knadle and Virendra R. Jadhav, “Proof is in the PTH – Assuring Via Reliability from Chip Carriers to Thick Printed Wiring Boards,” Electronic Components and Technology Conference, June 2005.
5. Kevin Knadle, “Reliability and Failure Mechanisms of Laminate Substrates in a Pb-free World,” IPC Apex Expo, March 2009.

Ed.: This paper was first presented at SMTA International in October 2011 and is reprinted here with permission of the author.

William J. Mack is test hardware development engineer at Texas Instruments Inc. (ti.com); This email address is being protected from spambots. You need JavaScript enabled to view it..

Multi-Fineline Electronix (MFLEX) and AT&S last week announced an agreement to share their respective printed circuit board technologies. Under the agreement, AT&S's high-density interconnect (HDI) rigid PCBs and MFLEX's flex board capabilities will be offered to respective customers, and the two will partner on rigid-flex technology.

MLFEX executive and PCD&F columnist Jay Desai spoke with editor-in-chief Mike Buetow about the new partnership.

Read more ...

Page 23 of 130