The latest reports from the local chapters.

Happy New Year! This month’s column highlights the Cascade chapter in the Seattle, WA, area. Also, after ringing in 2019, mark your calendars for two upcoming January shows in California (IPC Apex Expo and DesignCon), as well as this year’s CID and CID+ training and certification schedule.

Chapter Spotlight

by Cherie Litson, MIT, CID/CID+

This month’s spotlight is the Cascade chapter, which recently held a CID+ class at Lake Washington Institute of Technology (LWIT) in Kirkland from Dec. 4–7 (FIGURE 1). LWIT has partnered with EPTAC Corporation and Mentor, a Siemens Company, for a training facility focused on IPC certification classes. One of the full-time LWIT instructors, Joe Gryniuk, is an IPC-A-600 and IPC-A-610 instructor, as well as one of the principal instructors for electronic technician classes for more than 20 years. Thanks to Joe’s efforts, we have been able to present our CID and CID+ classes, host our Designers Council meetings, and support other IPC certification courses at LWIT.

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Figure 1. Cascade chapter’s latest IPC DC meeting.

Our CID+ class had four people enrolled who came from around the area. All who attended learned how board materials affected their designs, including EMI, EMC, impedance control, power distribution techniques, board stackups, and placement strategies in more detail than what was in the CID. Further, participants took the exam first thing Friday morning. This allowed time to attend the Designers Council “lunch-and-learn” meeting down the hall, and the Altium user group met afterward in the same location.

Starting our Altium user group was a huge success. There were many requests from our members who do attend the meetings for such a group. David Haboud from Altium came and did a short presentation on the new Altium 19 features. Then, we discussed how these features will affect how we use Altium going forward. We were very excited about the 3-D functionality and hope that it expands to be able to control more of the board-to-board signals. There was some skepticism about the new library functionality and how that will affect existing libraries. Most of us want to explore this in more detail at a future meeting. We’ll probably have another one around March.


The Cascade Designers Council started in 2001 with a small group of designers and Prototron, who were interested in networking and learning more about PCB design. Many of us had just taken the CID and were hungry for more information. We met at various places, including Prototron, Microsoft, Monsoon Solutions, SonoSite and Medtronics – anywhere we could find a meeting room. Some meetings were held at lunch and others in the evenings.

The chapter flourished for six to seven years, getting up to 80 members at one time, and then the crash of 2008 came. Many people moved to other areas and jobs or just retired completely. Some of us tried to get the chapter going again, but it just didn’t take until 2016. A new group of individuals stepped up and took on the task of making the chapter viable again. These individuals still run the chapter today: Tim Mullin, president; Paul Berndt, VP; Aubrey Moore, secretary; Jerome Larez, treasurer; and Cory Grunwald, webmaster (FIGURE 2).

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FIGURE 2. Board members (from left) include Paul Berndt, Tim Mullin, Cory Grunwald, Aubrey Moore and Jerome Larez.

They put in the time and effort to get the chapter registered in the state, reopened a bank account (more difficult than starting over), and reached out to the designer community again. Let’s admit it: Designers are “tough nuts” to open! It is always difficult to get us to move away from the computer and socialize, even when you wave pizza or sandwiches in front of our noses.

However, this group started to get that shell to open a little. First, they tried evening meetings (traffic sucks here, which is difficult), and then lunch meetings. Both proved to be challenging. They have given away wonderful door prizes, such as IPC standards, Prototron’s “Solder Mask Sampler,” books from Dock Brown and Doug Brooks, and field solvers from Polar Instruments. What will it take for you to step up and own your time and continued education as a designer?


There have been some amazing topics covered these last two years (including some by myself) [1]:

• “Flex Printed Circuit Fabrication” by Jerome Larez, MicroConnex (December 2018)

• “Achieving Cleanliness for High-reliability Boards” by Dock Brown, CRE (September 2018)

• “DFM and DFT, Part 2—The Risk-Cost Factor Defined and Quantified!” by Cherie Litson (June 2018)

• “DFM and DFT—How to Reduce Your Costs!” by Cherie Litson (March 2018)

• “Copper Roughness and How Roughness-related Loss is Calculated in Their Si9000e Field Solvers” by Geoffrey Hazelett, Polar Instruments (November 2017)

• “Understanding the Variables of Dielectric Constant for PCB Materials Used at Microwave Frequencies” by Dale Doyle, Rogers Corporation (July 2017)

• “Component Library Roundtable Discussion” Group discussion (May 2017)

• “Common Fabrication Concerns and Dealing with Today’s Controlled Impedances” by Mark Thompson, Prototron Circuits (January 2017)

• “The History of Signal Integrity Issues on PCBs—Four Stages of Problems and Solutions” by Doug Brooks, Ph.D. (November 2016)

• “Design for Reliability” by Dock Brown, CRE (September 2016)

• Trace and Via Currents and Temperatures—The Story that Grew and Grew! By Doug Brooks, Ph.D. (May 2016)

The Future

More great subjects and presentations are being planned right now. Some officers are getting busy with work and would like to have others step up this year and take on some of the responsibilities. We’re looking for a new webmaster and anyone else with ideas. We’d also love to have Rick Hartley come and do a two-day class for us in the future. Many other opportunities for learning and networking are coming in 2019. We really hope to have more people join us: current designers, engineers, manufacturers, software vendors, and those interested in PCB design. This area has so much potential! Visit for more information on our chapter and upcoming events.

2019 Training and Certification Schedule IPC Certified Interconnect Designer (CID)
      •  January 31–February 3: San Diego, CA
      •  February 26–March 1: Manchester, NH
      •  March 5–8: Santa Clara, CA
      •  March 19–22: Kirkland, WA
      •  April 30–May 3: Schaumburg, IL
      •  May 21–24: Pittsburgh, PA
      •  June 18–21: Kirkland, WA
      •  August 6–9: Baltimore, MD
      •  August 26–29: Markham, ON
      •  September 6–9: Santa Clara, CA
      •  September 19–22: Schaumburg, IL
      •  October 29–November 1: Anaheim, CA
      •  November 2–5: Raleigh, NC

IPC Advanced Certified Interconnect Designer CID+

  • January 31–February 3: San Diego, CA
  • April 16–19: Markham, ON
  • September 6–9: Santa Clara, CA
  • September 10–13: Kirkland, WA
  • September 19–22: Schaumburg, IL
  • October 29–November 1: Anaheim, CA
  • November 2–5: Raleigh, NC
  • November 26–29: Manchester, NH

Note: Dates and locations are subject to change. Contact EPTAC to check current dates and availability. A minimum enrollment of seven students is required for a class to be held.

Upcoming Events

IPC Apex Expo 2019

  • January 26–31: Meetings and courses
  • January 29–31: Conference and exhibition
  • January 31–February 2: IPC Designer Certification CID/CID+
  • San Diego, California

DesignCon 2019

  • January 29–31
  • Santa Clara, California

PCB West 2019

  • September 9-11
  • Santa Clara, California
  • September 6-8: IPC Designer Certification CID/CID+


• Controlling noise, EMI and signal integrity in high-speed circuits and PCBs

• Apr. 17-18 – Seattle

• Jun. 13-14 – Boston (Chelmsford), MA



1. IPC Designers Council Cascade Chapter, “Previous Meetings,” 2016–2018.


STEPHEN CHAVEZ is a member of the IPC Designers Council Executive Board and chairman of the communications subcommittee. To read past columns or contact Chavez, click here.





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