Or does it distract from the actual need of the signaling protocol?

Much engineering time is spent on designing differential signaling circuits to maintain a differential impedance between the two sides of the differential pair. A similar amount of time is spent measuring the final PCBs to ensure the differential impedance specification is met. The most common differential impedance target is 100Ω. A fair question is whether this impedance requirement is necessary. Once differential signaling is understood, it will be seen as unnecessary and distracting from the actual need of the signaling protocol. This article will clear up this confusion.

FIGURE 1 is a schematic of the original emitter-coupled logic (ECL) differential pair as used in early computer rooms to move ECL signals from one large gray box to another. It was not possible to ensure the ground connections between boxes were of enough quality to permit single-ended ECL signals to function properly. Differential signaling compensated for this ground offset as follows:

3-ritchey-diffpairs-figure-1











Figure 1. Typical ECL differential pair circuit.

In Box A, the single-ended logic signal A is converted into two identical but mirror image signals, A and A-. These two signals have two things in common. They are mirror images of each other, and they are tightly timed to each other. That is all they have in common. The designer’s goal is to ensure these two signals (A and A-) arrive at the two transistor bases in Box B with maximum fidelity. This is achieved by sending each on its own 50Ω single-ended transmission line with a parallel termination in Box B to Vtt, the termination voltage. Neither signal knows the other exists. They are two independent single-ended logic signals.

All the action takes place in Box B. The two transistors in Box B are called an emitter-coupled pair or current switch. Sometimes they are mistakenly called a differential pair. Their job is to switch the current, I, up one side or the other depending on the logic state being sent. It is necessary to ensure the voltage difference applied to the bases of the two transistors is sufficient to guarantee all the current is going up only one side of the pair. This is where the name differential comes from, not differential impedance – difference voltage. In ECL the difference voltage to achieve proper operation is about 15mV. The smallest signal sent from the driver in Box A is about 1000mV, permitting significant signal loss in the path.

However, the original reason for inserting a differential pair in the signal path is to compensate for ground offsets between Box A and Box B. This is achieved by placing a current source in the emitters of the emitter coupled pair. The collectors of the two transistors are also current sources. As a result of this, the emitter coupled pair is free to float up and down with ground shifts between the two ends of the signal path. For ECL, this shift can be as much as 1.5V.

How does a differential pair detect a logic state change? This is a good question. When the current changes sides between the two transistors in the emitter-coupled pair, a logic state change has taken place. This occurs when the two signals cross each other as they change levels. This means the receiver is a crossing detector. Therefore, the designer’s goal is to preserve the crossing. How does one do this? Ensure the two paths are the same electrical length. This is all that is required for successful differential signaling to operate.

From the above discussion it can be seen the differential impedance plays no role in successful operation of the differential pair.

FIGURE 2 is a simplified schematic of a low-voltage differential signaling (LVDS) differential pair. Notice the current switch in the right-hand side, just as there is with the ECL differential pair. Notice current flows into Vref from one side of the pair, and the same magnitude current flows out of Vref into the other side. As a result, during normal operation, the connection to Vref is not necessary and is omitted. This results in two 50Ω terminating resistors in a series. Often, money is saved by replacing them with a single 100Ω resistor. This is likely the reason it is assumed a 100Ω differential impedance is required. Provided the two signals cross exactly in the middle as shown in Figure 1, there is no need for this connection. However, at very high data rates, if this connection is missing and the signals do not cross exactly in the middle, for a moment there will be a need for current to flow into or out of Vref. If the connection is missing, the edges are degraded, sometimes enough to cause failure.

3-ritchey-diffpairs-figure-2











Figure 2. LVDS differential pair circuit.

At high data rates, if the Vref connection to the terminating resistors is missing, the signals will be degraded. In all modern high data rate differential signaling protocols, two 50Ω terminations are built into the receiver, and each is connected to “AC” ground in the receiver.

What about application notes that require “guard or ground vias?”

Some application notes require placing the two vias used to change layers for a differential pair close to each other and placing a “ground” via on each side of this pair. The reason given is the return currents have a path to change the planes on which they run. This sounds a bit arbitrary in the face of how a differential pair operates as described above, and it is. This is a solution to an imagined problem.

Recalling that each member of a differential pair is independent of the other, the first thing to note is they do not need to be routed side by side. The second is they are single-ended signals, just like all the other single-ended signals in a design. It is not necessary to put a “ground” via next to the layer-changing vias on single-ended nets. This is a fictitious rule that was made up by someone who did not do a proper job of analyzing the problem.

A Curious Observation

Many manufacturers of ICs that contain very high data rate differential pairs or SERDES (serializers/deserializers) have displays at design shows where the circuits demonstrated are connected with many single-ended 50Ω coaxial cables. These coaxial cables are isolated from each other, so there is no potential for a 100Ω differential impedance, and the circuits perform perfectly. These same manufacturers will publish application notes demanding a 100Ω differential impedance and tight coupling be maintained in a PCB. That the demonstration functions properly with single-ended 50Ω cabling validates the above explanation that differential impedance is not necessary, and designers should not spend time trying to achieve it.

Conclusion

Differential signaling does not rely on a differential impedance. Each of the two sides of the differential pair is a single-ended logic signal, like all other single-ended logic signals in a design. It is not necessary to route them side by side, although it is convenient to do so to keep track of them. In almost all cases, two 50Ω single-ended transmission lines of the same electrical length are all that is needed. If it is necessary to do so, the two members of a differential pair could be routed on different signal layers.

Lee Ritchey is considered one of the industry’s premier authorities on high-speed PCB and system design. He is the founder and president of Speeding Edge (speedingedge.com), an engineering consulting and training company, and will speak at PCB West in September; This email address is being protected from spambots. You need JavaScript enabled to view it..

Submit to FacebookSubmit to Google PlusSubmit to TwitterSubmit to LinkedInPrint Article