Printed Circuit Design & Fab Online Magazine - Effects of Plane Splits on High-Speed Signals, Part 1

A high-speed signal crossing splits of a reference plane can experience undesirable electrical impact.

Routing high-speed signals over slots of the nearby reference plane can cause undesirable effects such as impedance discontinuities (destructive reflection), EMI noise¹ and crosstalk. The reference plane may be a ground or a power layer.

One effective approach for gaining insight regarding the effects of plane split boundaries is to consider the nature of current flow. When a high-speed current travels along a PCB trace, an equal and opposite return current² flows in the reference plane underneath that signal track. This current returns in a manner to diminish the total impedance³.

At low frequencies this translates to minimizing resistance by spreading over every possible path. At high frequencies the return current crowds under the signal (on reference plane) to minimize inductance. An interesting way to visualize the current pattern on a reference plane is to define/model the geometry consisting of trace(s) and planes using FastHenry, a free 3D field solver. Then generate a set of current distribution files and plot them by applying Matlab commands⁴.

Although this approach has certain limitations it can provide useful understanding regarding the behavior of the return current. Hence, this technique was applied to simulate a trace with a solid reference plane and a trace-crossing plane split. For each case the trace length, width and thickness were set at 4 inches, 7 mils and 0.72 mils, respectively. The trace to plane height was 5 mils and the width of plane slot equaled 10 mils. The results for low frequency (f = 1.0 Hz) and high frequency (f = 100 MHz) excitations are presented by Figure 1 and Figure 2.

The results of Figure 1 verify that for low frequencies the return current (traveling from source to sink points) spreads⁴ across the plane, whereas at high frequencies the current is focused beneath the signal trace.

FIGURE 1. Return current distribution on a solid reference plane at (a) low frequency and (b) high frequency.

FIGURE 2. Return current distribution for a high frequency signal crossing a split plane.

Figure 2 demonstrates the high frequency current distribution for a split in the reference plane. FastHenry, in conjunction with Matlab, were again applied to model the geometry, compute the current distribution and plot the outcome. The outcome illustrates that the slot interrupts the path of the return current forcing it to find a way around the discontinuity.

One unusual feature of this visualization method is that sometimes current vectors⁴ point into empty space (plane gap). This happens because current vectors do not precisely exhibit the current flow at a given point.

Slot of any width can cause a current diversion, which in turn increases the loop area and inductance⁵ of the signal path. This leads to added crosstalk, and EMI and rise-time degradation. It is desirable to avoid slots in planes for high-speed PCBs, but they can occur in certain situations.

Sometimes ground layer splits happen because a board designer runs out of space on a regular routing layer and places tracks on the ground plane⁵ by cutting a slot in the plane layer for routing traces. Ground slots can also occur due to improper⁵ connector layout. A power plane with splits results when multiple powers are incorporated on the same plane layer. Power islands⁶ are among the most evident split-plane circumstances. The island’s boundary, or moat, defines a total break⁶ in the copper plane resulting in an isolated area. This approach is often applied to create unique power regions that connect either to the same voltage via a PI filter (composed of shunt capacitors and ferrite/inductor) or to a voltage different from the rest of the plane.

If a high-speed net is routed perpendicularly over moats, the signal trace will experience added inductance, degraded rise-time, crosstalk and EMI. Hence, an excellent rule is to avoid the routing of high-speed nets over plane splits; however, the complexity of modern high-speed PCBs may impose violations of this guideline.

Figure 3 displays a section of a multilayer board produced using the Cadence Allegro PCB Design Software. The PCB was examined utilizing Allegro Free Physical Viewer program by turning on the desired signal layer and its reference power plane with other layers turned off. The plane layer has a gap G due to boundaries of multiple power islands. Here the gap width is 20 mils. There are several traces (T1, T2, T3 and T4) of the signal layer routed over splits of reference plane. C1 and C2 outline two stitching capacitors (small valued caps with values ≤ 1 uF) to bridge the plane splits. The adverse effects of plane slots on high-speed signals crossing them can be minimized by implementing another plane tightly coupled⁷ via bypass and interplane capacitance. Such capacitance furnishes an AC path for the signal’s return current and supports the switching edges. The slots should not occur at the same location in both or all planes.

FIGURE 3. PCB signal traces routed over voids of the nearest reference power plane.

Stitching capacitors⁸, when properly placed, can reduce current loop area, lower impedance discontinuity, and minimize adverse effects on signal quality and EMI due to the crossing of splits. The ends of stitching capacitors need to be connected to each plane detached by the split.

The implementation method and location of capacitors play an important role in determining their effectiveness. In one study⁹, applying a 600 MHz clock with 300ps rise/fall times, a 0.1uF stitching capacitor was placed at one side of a signal bus (crossing plane splits) at distances of 1, 0.5 and 0.1 inches and directly adjacent to the edge-line. The signal waveform and overall radiation for these configurations were ascertained via simulation. It revealed that capacitors should be placed near (within 100 mils) the edge line. The capacitor became ineffective⁹ when located more than half an inch away. PCD&M

Dr. Abe (Abbas) Riazi is a senior staff electronic design scientist with ServerWorks (a Broadcom Company) in Santa Clara, CA. He can be reached at This email address is being protected from spambots. You need JavaScript enabled to view it..

ACKNOWLEDGEMENTS

Special thanks to Peter Arnold, Richard Kuo, Clement Yuen and Manvender Raghav for reviewing this article and furnishing valuable feedback.

REFERENCES

1. Doug Brooks, “Slots in Planes,” Printed Circuit Design, March 1999, PP. 36-37.
2. Howard Johnson, “Visible Return Current,” online newsletter, Vol. 8, Issue 08, 2005.
3. Brain Young, “Digital Signal Integrity Modeling and Simulation with Interconnects and Packages,” Prentice Hall, 2000, P. 413.
4. M. Kamon, C. Smithhisler, J. White, “FastHenry User’s Guide,” Sept. 26, 1996, PP. 32-38.
5. Howard Johnson and Martin Graham, “ High-Speed Digital Design; A Handbook of Black Magic,” Prentice Hall 1993, PP. 194-197.
6. Stephen C. Thierauf, “High-Speed Circuit Board Signal Integrity,” Artech House, Inc., 2004, PP. 95-98.
7. Lee Ritchey, “Examining Rules of Thumb,” Printed Circuit Design, Jan. 2000, PP. 36-38.
8. “High-Speed USB Platform Design Guidelines, Rev. 1.0” Intel, 2001, P. 8.
9. Juan Chen, Weimin Shi, Adam J. Norman, Ponniah Ilavarasan, “Electrical Impact of High-Speed Bus Crossing Plane Split,” IEEE International Symposium on Electromagnetic Compatibility, 2002, PP. 861-865.