NEVADA CITY, CA -- Demand for portable Internet connectivity devices such as cellphones, tablets, GPS devices, MP3 players and more is very strong, despite poor economic times. What these items have in common is that they all pack an enormous amount of functionality into a very small space.
To achieve this feat, these products must utilize more advanced packaging methods for the ICs inside the products, as it is the IC packages that hold the footprint to the PCB and thus determine the size of the PCB and, ultimately, the size of the final product. The packaging method of the chip also determines the speed and performance of that chip, as well as its battery consumption.
These devices are fueling demand for advanced IC packaging technologies such as system-in-package (SiP), stacked packages, fan-in QFNs, fan-out WLPs, and interconnection styles of 3-D and 2.5-D through-silicon vias (TSVs) and flip chip.
Stacked packages. Stacked packages are essentially a vertical multichip package. They come in many forms, including die stacks, package on package (PoP), package in package (PiP), TSOP stacks, QFNs, MCMs, and WLPs. Now found in all cell phones, stacked packages are in a high-demand market. Stacked package revenue will experience a 10% CAGR through 2015.
Through-silicon vias (TSVs)/3-D interconnection. Using 3-D interconnection with TSVs creates a die stack with the shortest interconnection distance, enhancing the characteristics of high speed, low power consumption, reduced parasitics, and small form factor. This interconnection style utilizes vias that go through the silicon to electrically connect one die to the next in a vertical stack, in place of wire bonds or other forms of connection. The identified potential markets for TSVs will climb from 35 billion units in 2010 to over 54 billion in 2015.
System-in-package (SiP). SiPs are a functional block, a system of electronics that combines functional units together onto a single substrate to enable the shortest electrical distance between parts for superior performance. This reduces the amount of traces going into and out of the package, enabling a more simplistic PCB for the final product and potentially reducing system costs. Revenue for SiPs will expand at a 5.4% CAGR through 2015.
Fan-in QFNs. To increase the reach of the QFN package, this involves extending the number of rows of leads from the usual one to two or three rows. This allows the number of package leads to extend into the hundreds, up from generally fewer than 50. Although the number of fan-in QFNs assembled currently is quite small, the potential is huge, with a projected CAGR of 63.1% for revenue through 2015.
Fan-out WLPs. Reconfigured or fan-out wafer-level packages (WLPs) were introduced in 2006. After devices are manufactured on a wafer, the devices are sawed and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This permits a larger surface on which to extend a redistribution layer, thus permitting far more I/Os than would be possible on the original smaller WLP surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board. Fan-out WLPs are expected to have CAGR revenue of 15.9% through 2015.
Applications for advanced IC packages. Cellular handsets are the primary handheld electronic gadget that everyone wants to own. Their use is spreading around the world, especially in territories too vast to support wired communication lines. Cellular handsets are growing at an 8.5% CAGR between 2011 and 2015, and smartphones, a subset of total cellular handsets, are growing at a 15.2% CAGR. Such rates definitely exceed that of the economy as a whole.
More information can be found on these topics and others in the new report, Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition, from New Venture Research.