A look at the geometry associated with plated through-holes in a PCB.
Application notes describe how to save layers in a PCB by routing two traces between pins on a 1mm pitch BGA. A leading FPGA vendor recommends this practice to use its very-high-pin-count FPGAs in a low-layer-count PCB. When this approach is used for a high-layer-count PCB, the result is often, if not always, very poor yields, and the board is unreliable when used in a system under actual conditions, as opposed to in a laboratory or a prototype built in a small volume by a specialty shop. The following discussion will illustrate why this approach results in unsatisfactory yields when volume manufacture is attempted.
To understand the space used to route traces in signal layers of a multilayer PCB (this also applies to four-layer PCBs), it is useful to look at how plated through-holes (vias) are created and the various requirements that must be met by the finished PCB. FIGURE 1 is an illustrated cutaway of a plated through-hole showing signal and plane layers.
Deciding the dimensions of the features in this diagram is often called padstack design. (This subject is discussed at length in Ritchey.1) The elements in a padstack design are the finished hole size, the drilled hole size, the size of the capture pad in a signal or surface layer used to connect to traces and component leads, and the size of the clearance hole or antipad in the plane layers. Things to account for are minimum thickness of copper plating in the hole, allowance for drill wander in the fabrication process, allowance for misregistration between layers of the PCB, minimum insulation thickness between plating in the hole and metal in the signal and plane layers, and adequate copper bonding between traces and the plating in the hole.
As will be seen, the dimensioning involved in designing padstacks is done from the edges of the drilled, plated hole to features inside the PCB or the drill size. Traditionally, the PCB design process begins with the diameter of the finished plated through-hole. The choice of drill size has been left to the PCB fabricator, and the size of clearance holes and capture pads in signal layers is large enough for ample room for a range of drill sizes. As the pitch between device pins has shrunk over the years, this practice has resulted in PCBs with poor manufacturing yields.
To solve this problem, the designer of the PCB padstacks must take charge of specifying the drill size, as well as the finished hole size. To get from finished hole size to drill size, one need only to take the finished hole size and add 4 mils (0.102mm) to the finished hole size. Then, designing the padstack can proceed from the drill size. (Once these dimensions are chosen, the drill size must not be changed. If the drill size is made smaller than that specified, the aspect ratio may grow too large, and plating may not be completed all the way through the hole. If the drill size is too large, the clearances to copper in adjacent layers may be too small, or the drill may break out the side of the capture pad on a signal layer.)
FIGURE 2 is a top-down view of a plated through-hole or via showing the clearance hole or pad in a power plane of diameter F. This is the minimum opening in the power planes needed to guarantee enough room for the drilled hole, the drill wander, and minimum insulation to the nearest copper in any layer, be it signal or power. FIGURE 3 shows an array of vias or holes spaced on a 1mm pitch. The web between clearance pads is what is available for traces on signal layers and for copper in the plane layers to conduct the current used by ICs and other devices on the PCB. (Note: If the trace width is the same as the web in the plane, the impedance of the trace raises several ohms as it passes over the array of holes under a BGA. To minimize this effect, the web should be wider than the trace by about 2:1.)
Calculating Width of Plane Webs and Routing Channels in Signal Layers
Clearly, the width of a plane web is the hole pitch minus the diameter of the clearance pad or hole. The question is how to arrive at the diameter of the clearance hole needed to satisfy all the constraints. These constraints are a drilled hole large enough to ensure proper plating; room around the drilled hole to allow for drill wander; and minimum insulation thickness.
Minimum drilled hole size. Determining the minimum drill size needed to ensure proper copper plating requires knowledge of the maximum aspect ratio of the drilled hole. Aspect ratio is defined as the ratio of hole length to diameter. This is covered in detail in Ritchey, Chapter 4.1 For now, the maximum aspect ratio for the top fabricators in the world is 12:1 for volume production. For the mid-tier fabricators it is 10:1, and for low-end fabricators it is 8:1. Of course, the minimum drill size is also influenced by the thickness of the PCB. For example, if the PCB is 120 mils thick and is built by a top-tier fabricator, the minimum drill size is 10 mils. For a mid-tier fabricator it is 12 mils, and for a low-end fabricator it is 14 mils. (As will be seen from the following analysis, with component lead pitches of 1mm or more, a 10-mil drill works well. For this reason, this is my default smallest drill size, even if the PCB thickness is less than 120 mils.)
Most high-performance PCBs designed today are 120 mils thick. This analysis will be for such a PCB built by a top-tier fabricator.
Allowance for hole wander. Drilled holes are often not exactly where they are designed to be for many reasons. Among them are the drill’s ability to locate the exact spot where the hole is to be drilled; layer shrinkage of the PCB during lamination; dimensional errors in the film used to image the layers of the PCB; and misregistration of the layers during lamination. All these errors add up to a position error for the drill that is often referred to as TIR (total included radius) of TID (total included diameter). Top-tier fabricators can hold a TIR of 5 mils (TID of 10 mils) across an 18" x 24" panel – the most common panel size.
Therefore, we must allow 5 mils per side of the drilled hole for drill wander. This produces what is called a hole shadow the drilled hole casts all the way through the PCB. This shadow defines where we might find copper connected to a via or trace. We must keep away from this shadow in all layers by a distance defined by the insulation requirement for the PCB.
Minimum insulation requirement. Most laminate has a breakdown voltage on the order of 1000V per mil of thickness. Many systems require a minimum breakdown voltage or hi-pot test of at least 500V, and most Internet or telco products require 2000V. Being conservative, it is good to design for the more difficult requirement of 2000V. This requires a minimum of 2 mils of dielectric between opposing circuits or between traces or planes and plating in the hole. This requires the clearance hole diameter to be 4 mils larger in diameter than the hole shadow.
The problem with this small dimension is it does not account for the chemistry involved in etching, cleaning and plating wicking along the glass fibers in the weave of the laminate layers. FIGURE 4 is a microsection of a plated through-hole showing wicking along the glass fibers. To lend some scale to the photo, the copper layers are 0.5 mils thick. Some of the wicking is as much as six times this, or 3 mils. This wicking is conductive. Therefore, it effectively increases the diameter of the plated through-hole by this amount per side, or 6 mils total.
Adding the 2 mils per side required for insulation and 3 mils per side for wicking, the total insulation thickness required to meet the insulation requirement is 5 mils per side.
Adding It All Up
Using the above information, it is possible to determine the plane web available for conducting current and space available for routing traces between pins of a 1mm pitch BGA. For the 120-mils-thick PCB, the minimum drill size is 10 mils. Referring to Figure 2, the diameter of the finished hole size is 4 mils less than this, or 8 mils nominal. The hole shadow is the 10-mil drill plus 10 mils for hole wander, or 20 mils. The clearance hole in a plane is 20 mils plus 10 mils for insulation allowance, or 30 mils.
The hole-to-hole distance of a 1mm pitch BGA is 39.37 mils. Subtracting 30 mils from this results in a web width or trace routing channel width of 9.37 mils. This is ample room for a 5 or 6 mil trace. If one attempted to route two traces between holes (assume they are 4 mil traces with a 4 mils space), the total width required would be 12 mils. Clearly, one of the requirements spelled out above would be violated, and the PCB would suffer from yield problems.
Preventing breakout of capture pads on signal layers. The connection between a trace and a plated through-hole is made by flashing a pad on the signal layer connected edge onto the plating in the hole. This can be seen in Figure 4 on the second layer from the top. The size of this pad has a direct relationship to overall reliability of the assembled PCB. If the contact between the trace and the plating in the hole is just the cross-section of the trace, a butt connection, this bond is not strong and is likely to be broken during soldering or rework, resulting in an intermittent PCB. The solution is to make the capture pads on signal layers larger than the hole shadow by enough to guarantee no butt connections occur, no matter where the drilled hole lands within the shadow. This allowance is called an annular ring. Depending on the reliability level of a product, the annular ring may be 1 mil, 2 mils or 0 mils. (IPC Class 3 is 2 mils.)
Products intended for the consumer market have lesser reliability requirements than those destined for computers, military or telco equipment. In the latter case, the minimum annular ring for a capture pad in a signal layer is 1 mil. This means these capture pads must be larger than the hole shadow by 2 mils. In the above analysis, the hole shadow was calculated as 20 mils. This requires a capture pad of 22-mil diameter.
When the insulation requirement of 5 mils per side is added, the result is 32 mils. Subtracting this from the 39.37 mil pitch of the BGA, one arrives at a useful space for traces of only 7.37 mils. Clearly, there isn’t even room for a single 6 mil trace, much less two!
Note: Often, when the capture pad is not large enough to prevent breakout, a fillet is added where the trace enters the capture pad to prevent a butt connection. This is often called “teardropping."
Nonfunctional pads. When early CAD systems created artwork for internal signal layers of a multilayer PCB, the same pad artwork used on outer layers was used for innerlayers. This resulted in pads on every internal signal layer, even when there was no signal connected to the hole on that layer. As experience was gained fabricating multilayer PCBs, it was discovered shorts often occurred between these nonfunctional pads and traces passing by. The solution was to remove these nonfunctional pads. Most fabricators do this as a standard practice. Newer CAD systems do not put nonfunctional pads in the artwork.
The notion removing nonfunctional pads creates room for more traces is not true. The size of the nonfunctional pads is the same diameter as the useful pads whose size was calculated to permit clearance for hole wander and insulation.
The features associated with a drilled hole in all layers are commonly called a padstack. In this example the pad stack is as follows:
Drill size = 10 mils
Finished hole size = 6 mils nominal
Capture pad size = 22 mils
Annular ring = 1 mil
Clearance hole = 30 mils
Web with 1mm pitch = 9.37 mils
Maximum trace width = 5.37 mils
To preserve routing space throughout the signal layers, the minimum pitch of routing vias or component holes for surface mount parts is 1 mm. Any via or hole for connecting a lead of a surface mount part to an internal layer should use this pad stack and this hole pitch.
All other plated through-holes should have their pad stacks designed as follows:
Drill size = finished hole size + 4 mils
Capture pad size = drilled hole size + 10 mils + allowance for annular ring
Clearance hole size = drilled hole size + 20 mils
Minimum hole pitch = (d1 + d2) +18 mils + minimum web requirement (usually no less than 7 mils), where d1 and d2 are the two different hole sizes.
Some observations. From the above it can be seen routing two traces between pins of a 1mm pitch BGA will result in a low-yield, unreliable PCB. Once it is agreed it is only possible to route one trace between pins, provided the trace width is 5 mils or less, it is possible to specify a minimum drill size of 10 mils. There is no good reason to specify a smaller drill size and the difficulties it entails, especially potentially unreliable plating.
If one is fortunate to have access to 50-mil pitch (1.27mm) BGAs, the space available for traces is 50 mils less 30 mils or 20 mils. This is plenty of room for two traces between pins and the space needed to separate them. When picking between a 1mm pitch component and a 50-mil pitch component, the choice is clear. IC manufacturers would do their customers a great service to stick with 50-mil pitch BGAs when the pin count is high. They do their customers a grave disservice when they specify 0.8mm pitch components.
1. Lee Ritchey, Right the First Time: A Practical Handbook on PCB and System Design, vol. 2, 2003, Appendices 6, 7 and 10.