VTOS DDR standalone DDR verification tool now supports board designs using Sitara AM335x processors from Texas Instruments. Permits configuration, verification, and tuning of DDR memory for board designs. Integrates with vAccess for automated production test. Provides simple user interface and working board examples for configuring and tuning DDR memory in minutes. Can be tailored for custom board designs. Comes with memory part configuration settings, which also can be tailored to match new memory parts. Flexible user interface alters any memory mapped register, and run-time scripting allows custom testing and tuning. With a JTAG programmer, verifies DDR memory for new board designs that don’t have software loaded.
Kozio, www.kozio.com/content/vtos-ddr
CADStar Essential schematic and PCB design tool suite offers a single design environment with a common GUI for core PCB design activities such as schematics, library creation, routing and export for manufacturing. The complete schematic to PCB design flow supports up to 1,000 pins on four layers with an effective cost of $1 per pin. Supported by downloadable self-teach support material that incorporates links to video files to illustrate key features. Targets novice and basic designers and priced at $999.
Zuken, www.zuken.com/cadstar-essential
Primera LP130 laser markable labels are for high-temperature and harsh environments. Available in UL approved XF-537 for printed circuit board applications, and GMW14573/GM6121M tested XF-670 for low surface energy applications. Can be ablated and cut by a wide variety of low power CO2, YAG, fiber and UV lasers to produce high contrast linear and 2-D barcodes and alpha-numeric characters. Are designed to be used on desktops and workbenches. Contain a high-power fiber-coupled laser module. Are for automotive, aerospace, IUID, PCB and UDI applications.
Polyonics, www.polyonics.com
Sherlock Automated Design Analysis software now recognizes the IPC-7351B naming convention for standard surface mount technology land patterns and the working draft of IPC-7251 for through-hole land patterns. The IPC requirements provide generic requirements to be used for the surface attachment of electronic components, as well as surface mount design recommendations for achieving the best possible solder joints to the devices assembled.
DfR Solutions, www.dfrsolutions.com
Enhancements to existing Allegro commands include Enhanced Back Drill for back-drilling high-speed boards. Automatically creates route keep-outs for area contained in back-drill path. Dxf2mcm, for Cadence ADI/SiP tools for IC package design, imports any DXF drawings or files and creates intelligence.
dalTools, www.daltools.com
CITS880s controlled impedance tester now features Launch Point Extrapolation (LPE) for fabricator-level instantaneous measurement and control on high-speed PCBs. LPE is a line-fit technique deployed on thinner traces which exhibit significant slope arising from DC and AC resistance along the trace. LPE “projects the impedance back” to a point close to the start of the trace where the influence of the DC and AC resistance on the measurement is minimal. In conjunction with 2D field solvers, is said to yield significant improvement in correlation between measured and modelled impedance. With high-speed IPS probes, tests trace lengths 2 to 3" shorter than previous versions. Outputs reports using novel software or in Excel-compatible format.
Polar Instruments, http://www.polarinstruments.com/