PathWave ADS 2023, for high-speed digital (HSD) design, comes with new Memory Designer capabilities for modeling and simulation of next-generation interface standards such as DDR5.
Ensures rapid simulation setup and advanced measurements while providing insights to overcome signal integrity challenges. New Memory Designer constructs parameterized memory buses using new pre-layout builder, to show system tradeoffs that reduce design time and lower product development risk for DDR5, LPDDR5/5x, and GDDR6/7 memory systems. Accurately predicts closure and equalization of the data eye: minimizes impact of jitter, ISI and crosstalk using single-ended I/O (Input-Output) buffer information specification algorithmic modeling interface (IBIS-AMI) modeling with forwarded clocking, DDR bus simulation and accurate electromagnetic (EM) extraction of PCB signal routing Shortens time-to-market with a single design environment that enables pathfinding in pre-silicon digital twins to address current integration requirements such as forwarded clocking and timing, IBIS algorithmic modeling interface (IBIS-AMI) modeling and compliance tests and future challenges like single-ended Pulse Amplitude Modulation 4 level (PAM4), for exploration of DDR6.
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