The relative permittivity for FR-4 is just that: relative.
Ed.: This is Part 3 of a three-part series on preparing for next-generation loss requirements.
Last month, in Part 2 of this series, I outlined the means by which insertion-loss requirements are determined. Here, I’ll suggest a better method for obtaining accurate Df numbers without having to go to the trouble of building test boards.
A longtime PCB industry technologist asked me recently, “What’s a good Dk (dielectric constant) number for FR-4?” As the interest in signal integrity (SI) was growing roughly 25 years ago, it started to interest me that many SI practitioners considered FR-4 to have monolithic properties. The question reinforced that some still hold that view. One might say the relative permittivity (ϵr) of FR-4 is 4.3. Someone else would say 4.1. A third says they always use 4.0. As I read up on it, I realized it varies with frequency, resin content (as a percentage, with the inverse being the glass percentage), and the resin system. At lower frequencies, static numbers for vanilla FR-4 were probably fine for impedance calculations and signal integrity, but those days are far behind us at this point.
Looking at the hundreds of materials in the Z-planner software library, there’s a clear relationship between Df and Dk values. FIGURE 1 summarizes this relationship, along with the bullet list below:
So far, so good, but this is where the discussion gets interesting. I wrote a good bit about this, as published in this space between December 2018 and February 2019, so I’ll try to avoid duplication. As I’m unpacking from a pair of trade shows last month, I’m recalling a discussion with a laminate manufacturer that mentioned they use four different fixtures to measure Dk and Df up to 20GHz.
The values represented above come from eight different manufacturers, using a smattering of 12 different IPC test methods measuring Dk and Df. As a result, there’s no way to correlate Dk and Df values directly across the different laminate vendors that use different test methods.
To make matters even more confusing, laminate manufacturers may use:
PCB fabricators typically use their own Dk fudge factors, based on actual circuit boards, in which they attempt to remove copper effects in order to backwards-engineer Dk and Df values. And multi-gigabit Serdes signals will often be planned using Dk values at 1GHz. And we haven’t even discussed temperature impacts or that half the Dk values from laminate manufacturers are in the x-y plane, which a signal will never see!
In this environment, Dr. Eric Bogatin introduced me to Dr. Don DeGroot of CCN Labs, and through meetings across multiple industry conferences we found we share an interest in developing what we called an “apples-to-apples” dielectric-characterization methodology that basically took the best practices from the most common IPC test methods for dielectric characterization, combined with a commercial stackup-design solution.
Measurement comparisons. As part of our journey toward the “ideal” dielectric-measurement system, our goal was to gain insight into how closely published copper-clad laminate (CCL) manufacturers’ table values for Dk(f) and Df(f) correlated to our calibrated measurements of the dielectric’s Dk and Df from 1 to 20GHz. What we found was that within specific CCL manufacturers, published Dks varied by +/-10% from our measurements – a 20% variation from minimum to maximum. For signal-integrity purposes, it would be advantageous to remove this additional source of uncertainty, both during new product introduction (NPI)/prototyping activities and in volume production.
Dk and impedance. To provide an idea of the impedance implications associated with accurate Dk values, consider a symmetrical differential stripline model with 5-mil thick dielectrics and 5-mil wide traces.
Published: Incorporating a published Dk of 3.74 produces a 50.8Ω simulated single-ended impedance and a 97.2Ω differential impedance on 12-mil spacing.
Measured: Using the measured Dk value at 10GHz for a laminate in our study, the simulated single-ended stripline impedance result was 48.5Ω, with a 92.8Ω differential impedance.
Depending on frequency and other factors, the design may be able to survive a 4.5Ω differential impedance gap, but this difference will be in addition to other tolerances and manufacturing variations you must account for, which can pose problems if all the variance works in the same impedance direction. And impedance mismatches – assuming you were targeting 100Ω differentially – cause rise-time degradation that contributes to eye closure, as discussed last month. SI simulations based on the questionable Dk values will be inaccurate. My view is giving away this accuracy when it’s so easily avoidable is not good design practice.
Df and insertion loss. One of the more significant findings in our research is the degree to which published Df values tend to diverge from our calibrated stripline-resonator results. These differences vary in magnitude, but always in the same direction: Our calibrated stripline-resonator measurements were always higher than vendor-published values. The Df differences were particularly striking at 1GHz, ranging from 33% for one material to 200% for another common material.
To get an idea of the propagation-loss implications for underestimating Df, consider the same stripline configuration noted above, assuming copper foil with Rz=2µm roughness on the laminate and processing on the prepreg side that results in Rz=1.5µm.
Published: Incorporating a published Df of 0.006 produced an insertion loss of 0.72dB/in at 10GHz.
Measured: Using the measured Df value of 0.010 at 10GHz for a laminate in our study resulted in an insertion loss of 0.88dB/in at 10GHz, as shown in FIGURE 2.
Multiply these values by a 10" interconnect length and we’re talking about a 1.6dB difference. That’s not a long signal path, and the unplanned loss delta is enough to cause headaches, especially for longer run lengths. There’s a cost element as well. In this example, you paid for 0.006 and received 0.010. That’s a caveat emptor moment. The only foolproof way for engineers or PCB fabricators to know they’re getting the loss performance they’re paying for is to measure dissipation factors at frequencies of interest on their own test benches and in the production environment.
Parting thoughts. As engineers and PCB designers are preparing to implement next-generation technologies, we no longer have reason to employ multiple dielectric-characterization methods or fixtures when moving from one frequency to another, to use different methods for Dk and Df, using in-plane measurements that a signal will never see, or using different test setups among laminate manufacturers, PCB fabricators and OEMs.
At DesignCon, we unveiled the first set of low- and ultra-low loss laminate measurements from this system, called “Z-field,” shown in TABLE 1. The system itself, a combination of hardware and software, is shown in FIGURE 3. Results should be similar to what would be expected from a well-calibrated Bereskin Stripline system (now IPC-TM-650, no. 2.5.36), while obviating the need for IPC-TM-650, no. 126.96.36.199, 188.8.131.52 and 184.108.40.206. Game-changing!