W.L. Gore & Associates, Inc. introduces GORE QSFP, copper cable assemblies for high-performance computing (HPC), enterprise network and network storage markets. It is reported that signal reliability is improved at speeds over the standard InfiniBand QDR data rate of 10 Gbps/channel.
 
Benefits include low latency, decreased jitter and maximum signal eye opening. Signal reliability is enhanced over the InfiniBand QDR data rate of 10 Gbps/channel. The cable is constructed with low dielectric materials that improve bend radius over longer distances in small cross-sectional areas.
 
The assemblies are offered with GORE EYE-OPENER Conductor technology for higher data rate and longer distances. According to the company, the cables are designed to “reach further than other cables” and will lighten cable management in tight spaces because of their smaller size.  
 
www.gore.com

Silicon Laboratories, Inc. introduces the Si474x automotive AM/FM radio receiver IC. Reported to be the smallest and most fully integrated, the receiver supports worldwide radio band requirements, including weather bands, short wave and long wave. External component count and the associated costs have been reduced 40%, according to reports.
 
With a printed circuit board (PCB) footprint less than 4 cm, the single-chip solution is packaged in a 4 mm by 4 mm package. It consumes less than 1/10^th the power of standard tuner ICs, and automotive-grade quality is provided.
 
The product can support integrated algorithms, impulse noise event detection and blanking and advanced audio behavior in adverse radio environments. The features are programmable and can be customized for manufacturer and model specifications.
 
www.silabs.com

EMA Design Automation introduces TimingDesigner v9.1. The standard tool for interface timing design now has the ability to generate SDC timing constraints from timing diagrams. Users are able to visually define requirements and generate SDC to drive, place and route.
 
The SDC support also adds the ability to interface with FPGA and ASIC design flows. With focus on the Altera FPGA, graphical timing analysis features enable the development of SDC timing constraints for Altera devices. General productivity enhancements and updates are included. 
 
www.ema-eda.com