Design News

MAYNARD, MA – A paper written by Signal Integrity Software Inc. (SiSoft) and co-authored with Cisco Systems has been nominated as a Best Paper Finalist at DesignCon 2009.
 
“A Simple Via Experiment” presents an analytical model for understanding and predicting behavior of via structures, correlated to lab measurements. Theoretical, 3D field solver and measured data will be presented for an experimental via structure designed so that the experiment can be easily repeated.
 
Dr. Michael Steinberger of SiSoft will present the paper on February 3.
MUNICH, GERMANY and WESTFORD, MA – Zuken is offering a free download of CADSTAR 11 Schematic Design Tool until March 31.
 
As designs become more complex, the need for data transfer and communication between members of a design team is crucial. By providing a single design tool environment, Zuken anticipates users will be able to process designs quickly and at lower costs.
 
The software can be downloaded at www.zuken.com/CADSTAR, users will need to provide a MAC address to obtain a license.  
 ATLANTA – Intercept Technologies Inc. announced that National Instruments has chosen the Pantheon and Mozaix RF design tools for its latest generation of RF instruments. 
 
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MUNICH, GERMANY and WESTFORD, MA – EID has adopted the CR-5000 design platform by Zuken. EID will use the technology for its complete front to back-end methodology, including signal integrity simulation.
 
EID believes CR-5000 will decrease verification run time and increase layout efficiency on complex development. “Without this kind of unified design and analysis environment we would never have achieved the fast development cycle-time needed for our most demanding projects,” said José Taborda, head of CAD department at EID.
SOUTH PLAINFIELD, NJ Sharon Trueman has joined the design management team at R&D Circuits. As the senior applications engineer, she will be responsible for customer applications assistance and process development.
 
Trueman brings over 20 years of experience in the semiconductor manufacturing and test environments. For the last 8 years, she has focused on ATE load board and probe card design, holding key positions with several ATE design companies. She will be based at the Design Center located in Meza, AZ.
SANTA CLARA, CA -- Sigrity, Inc. announces the release of Channel Designer, an analysis solution that offers the flexibility and accuracy required for high-speed serial links.

"Our customers have found that designs with high-speed serial links operating at multi-gigabit speeds require more than traditional analysis," said Dr. Jiayuan Fang, president of Sigrity. "It is essential to accurately predict bit error rate to ensure a robust implementation that can handle anticipated jitter and noise levels. With millions of bits of data to be considered over a wide frequency spectrum from DC to tens of gigahertz, it can be extremely challenging to obtain reliable time-domain simulation results from band-limited channel models. Channel Designer provides unparalleled precision, and builds on Sigrity's long-standing strength in S-parameter handling for accurate system-level transient simulation."

According to Sigrity, the analysis solution provides support throughout the process, from feasibility studies through design verification. The channel analysis output includes 2D and 3D eye diagrams, along with bathtub curves, for accurate bit error rate prediction.

The channel design capture environment includes a net-based, block-wise schematic editor for designs ranging from a single net interconnect to an entire bus traversing multiple boards. The analysis solution provides high simulation accuracy for accurate transient simulation for designs from DC to 10 gigahertz and more.

The analysis solution uses an industry standard IBIS Algorithmic Modeling Interface (AMI) transmitter and receiver model plus unique capabilities such as cascaded model support to simplify the flow.

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